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Sun, 21 Sep 2025 23:06:49 -0700 From: Tariq Toukan To: Saeed Mahameed , Leon Romanovsky CC: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , Tariq Toukan , "Mark Bloch" , , , , Gal Pressman Subject: [PATCH mlx5-next 1/2] net/mlx5: Add IFC bit for TIR/SQ order capability Date: Mon, 22 Sep 2025 09:06:30 +0300 Message-ID: <1758521191-814350-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758521191-814350-1-git-send-email-tariqt@nvidia.com> References: <1758521191-814350-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0DE:EE_|DS4PR12MB9659:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a1e616d-cc6d-419e-1bac-08ddf99e44cf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Guz8gqJOSbSb6Tniagf2I+Mottnzq6JYENfLeBhxgNPVsyyvh8I3uSneh4jV?= =?us-ascii?Q?GnhyTZVJUTrlK+MfqdghIJr2SFIM1vygxHYhKknBFKwFQzQvxQJjQCdQ8y+2?= =?us-ascii?Q?s9h1bKXTsJ/7XHoeMgbGweTJRnQ7/sV/IDToewfMJQROdKSGNzRDxKX65m6g?= =?us-ascii?Q?h8iaJ91XSx5KkYYJE+gAeGKUWZkwdf9an0E/LF5mQpzpIgpuEC4LKdumLbAB?= =?us-ascii?Q?5Xv/Gal8ZlycmykPprwzczG4o1YQH0ivwjuNY8XeibpcqSFThr3ksjMORalb?= =?us-ascii?Q?NfWSR7ZjXymyxzj13jblJvrX/N5zP0/yfwBOPbUwMK23rzXz4Qh9D7OC1qlA?= =?us-ascii?Q?ZjSWBzeBBZz+XrT74YqGxVx0c3CmWhI9lZJdbPGU5n6jiZIBeFi2H/HqbZOD?= =?us-ascii?Q?UsA/6dlDxJxqrUc3amiFxCRKtqLiQ+SU4VUOLHYVCrMHQwtOLgufhggHVW0l?= =?us-ascii?Q?YlBA5CcIfGSRzMmDGj0vXyyZa1p/bHEZOyb8mTAs8xw47RC/xziVVLSN+YLS?= =?us-ascii?Q?o11jwvvJDn8oUx1BYPqlXyjpRl2W/4QRxaUeOuIlOb7LTMQpPqt41vJgFHo9?= =?us-ascii?Q?nWvZI+TztJ+Tm1+esgrtqaHjkV5mOdTQNVhFYomS24nMCYerlUYn3cqS6+d3?= =?us-ascii?Q?FNoJefxc5vcgI+XG4C6J0IU5PY4+EMZnrVTG3+76Q6tNs2Icewxmu/emVXU+?= =?us-ascii?Q?LKy+vMtjp7fPTVQSI9NxLIQ1YDpoE/0ETdwQGNI16BtmBdnrMYBft4qlCHMC?= =?us-ascii?Q?FX35ovUMO170miCw0vvhMSPqYztE0NYYxugEiATmj4Tj/kbAuKcNI9U5EjUM?= =?us-ascii?Q?65Zgbmlj3xmJenaTzlqQZfmtLqkWryS1/BULeEaIQ1eegQHpP91FQEz81dUI?= =?us-ascii?Q?7k0u0FRd9LhMF9vJ7qOrUap+PI28LVhFPL2eStGOZq0GpDHUX/AfxqPOSDrb?= =?us-ascii?Q?6YLWrq7zELG0IyPrvlWHtqp6SbsdTs1e9sEMZ1iqvbYi6uxyyWHdAC6PRhOE?= =?us-ascii?Q?kZ8ftCtT78As8aef0QR3EaFRpTyKX+nM1E7gexYdaWOLAzEr6otQlyQZHnZh?= =?us-ascii?Q?7C5diDL82TCpSCKshhiqVaHgAEhkHSe0lPwO4dldVaEgrNufVRVzLOsDFX9O?= =?us-ascii?Q?7axM8WVMHzL/5MRjhhnr7W6BAX1fAmaUI6l+YhMvjeM/5YTw29m2lw3mQvah?= =?us-ascii?Q?EiRUh3dl1wZE5TVKW7fO7ovyT44E6/u7tE/6t/YlRG4/H24g1cBM8hvMLl8e?= =?us-ascii?Q?5s/OYVevjTKCDD+jHbXKSs9UsNTuWy+gyX3un3SiYB2FbWMIb7JtZFJwteMn?= =?us-ascii?Q?GGN4UBzhNXX2l7AE8XiZeAvvCZMHrlXDY4UTPShz0HCwXyADdoVsPK62Jg7G?= =?us-ascii?Q?4mZJO6Wxq4yQY0GZWWn/W/ZSDQe0aXzm60074PrfLBKs4WLd+kZT6ug27o3B?= =?us-ascii?Q?rEDUkMFRjd3tI1iL+G8jBUXAT5hmElRQll1xpLr90sJCebA+9zc+LEV1RqVA?= =?us-ascii?Q?QiTVwKMj+3oZ3/AcTGSENQ1KZVZ46pBQWIAY?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2025 06:07:10.9287 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a1e616d-cc6d-419e-1bac-08ddf99e44cf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9659 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Before this cap, firmware requested a certain creation order between TIR objects and SQs of the same transport domain to properly support the self loopback prevention feature. If order is not preserved, explicit modify_tir operations are necessary after the opening of the SQs. When set, this cap bit indicates that this firmware requirement / limitation no longer holds. Signed-off-by: Tariq Toukan Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea --- include/linux/mlx5/mlx5_ifc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 0cf187e13def..c0f5fee7a4a5 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1895,7 +1895,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { =20 u8 reserved_at_2a0[0x7]; u8 mkey_pcie_tph[0x1]; - u8 reserved_at_2a8[0x2]; + u8 reserved_at_2a8[0x1]; + u8 tis_tir_td_order[0x1]; =20 u8 psp[0x1]; u8 shampo[0x1]; --=20 2.31.1 From nobody Thu Oct 2 04:45:15 2025 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013021.outbound.protection.outlook.com [40.107.201.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 055F22ED842; Mon, 22 Sep 2025 06:07:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Miller" , Tariq Toukan , "Mark Bloch" , , , , Gal Pressman Subject: [PATCH mlx5-next 2/2] net/mlx5: IFC add balance ID and LAG per MP group bits Date: Mon, 22 Sep 2025 09:06:31 +0300 Message-ID: <1758521191-814350-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758521191-814350-1-git-send-email-tariqt@nvidia.com> References: <1758521191-814350-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0DF:EE_|CH1PPF5A8F51299:EE_ X-MS-Office365-Filtering-Correlation-Id: 7a5d00b2-a765-4321-2879-08ddf99e46e6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ZVbXYi7hf/w0TD/cEfjWiqIXdBS7jpz0An7Bl9KeMXbIgaBBb3EThUuQhbN2?= =?us-ascii?Q?rhNNUK0iD+jvOpkHNeD+OBjuC+scf6y+WWzkzTfcrBvb22shC+/NIE3wjazD?= =?us-ascii?Q?7yX2rET1WgUbKzCAenEgbzntE33n9FYQ1lxmVYQyQb9JiJw8jvwu28gYzG1x?= =?us-ascii?Q?LRq6UAuO56w7EmcCd5kSBx7W1FCsNdxDsEVc8WfIU1MhjpYe4j3q02H7SZT3?= =?us-ascii?Q?5KGp4UA/M4OwZNuutCzGqjD1S5C3/4J23Lfu17WKUXInItXtPOwUT54VBV01?= =?us-ascii?Q?9KaVsxBbFJikXRMoH9C9Q3CowLOVlRKpyb0PubriK55MdcHTaqNELPk1A7yp?= =?us-ascii?Q?+AQf9R7r7/8l7c51VSvQcUtNsqwgcFY4pNZ8NGH2axXIcYfMtt3jOyGNfVWL?= =?us-ascii?Q?OQJjGD9tWiJbOgggMtm2ctg1hKanLMfz8I4D5dY1cWocTMkx2kapBGo6RVUU?= =?us-ascii?Q?SqKHmyji59UepQsETNVsaowzsjmWjJfZDhrOcHzPrGOc00tC2+bxjJCbBYqg?= =?us-ascii?Q?JRWeyTqwGYrQWSL0elGXB23jrKGD2xxloVDj3bUmMkU7qsteh5Qi7Xaf/jtp?= =?us-ascii?Q?pq4Zr58DOAPYe+BJvex6I9roLn2wQiXlZRDlaBZmk5S/uPxO+fpzKdQgyi8b?= =?us-ascii?Q?3pB1XqzwshoFOE3/KapMJC7BBWME41YSSIVQz9CsZgJ2S+rIlLvUQVwE+VEs?= =?us-ascii?Q?4M/s2VjI/FQSP2TPMI34dLkHVxyzuG8EimXTv0IrxvQYk6+nwnmADvfEDdx5?= =?us-ascii?Q?fWJwlVrWgsUk/y7Ou8IxYpLFivgJNF8B/T/3j/7r6hzLUO1hUVGt91NX5qW/?= =?us-ascii?Q?WFAXuq7y2r3GzbOS0nc6l6zC/9IoG1s/kfk4T0QyuHgNZpLlxiW4gU1RFw0q?= =?us-ascii?Q?718Mdymz6MqCy0XLCnWFA43IFBDhx+GAKucQf1ifyEa8BPZELIWaNbwcbHbA?= =?us-ascii?Q?WoplcP7qkxJCIu8d6mn+MQe7qltrZqKLay0JFGz5MQm10jHmPRpx02DM2Gni?= =?us-ascii?Q?A1Dg3ibDrZZ5Cm6pqrvVXhzuz4I7m7uSicm5P5AKd32knLV00LLedgM2XvoC?= =?us-ascii?Q?sKq7VBA8S+yO+h4thPsO3JGaKWKFbqbb3WOp96/m1wugKeK8+5VM0p0k6GE9?= =?us-ascii?Q?3RW1RZzRXZhjQBm9JSciNoIL4YW78wXFdeGL0/AsEvbuFpXI9pmlFoVv4FKX?= =?us-ascii?Q?PMBr2GQExYnL4om28I/8rzvkJ9s+3auzgq1kZK8Is0/Ie4IFLKHylSA7OpTk?= =?us-ascii?Q?qgDJRV7EuhKkRwVboXct1uOvoM12jqcjzT3avtM4aZZjP+Su1a+7KDGQcpke?= =?us-ascii?Q?1F2Bko3/oqEf4RxCYYa0u9b1KpTnoiLpv9Kp7oFEILF6OrJZYWqCqTCt4s2d?= =?us-ascii?Q?P/WCvvZRr8yTYMSPVWLrnreZsAg7Gi4gkWSmumr24xN36R3opb0tw6gfMy2W?= =?us-ascii?Q?Z+oF8SXvxJzFFIn1/OkrF6+f5z7zQ2GHrv1v2QNPs/nFxgDq7FQLSjf+OQLm?= =?us-ascii?Q?Vy6LmaG1QEvpuJtX1/F39Cg0YX8HZCvfMuh6?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2025 06:07:14.4321 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a5d00b2-a765-4321-2879-08ddf99e46e6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF5A8F51299 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mark Bloch Add interface definitions for load balance ID and LAG per multiplane group functionality. This patch introduces the hardware capability bits needed to support balance ID in multiplane LAG configurations. The new fields include: - load_balance_id: 4-bit field for balance identifier. - lag_per_mp_group: capability bit for LAG per multiplane group support. These interface additions are prerequisites for implementing balance ID support in the MLX5 driver. Signed-off-by: Mark Bloch Reviewed-by: Shay Drori Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index c0f5fee7a4a5..07614cd95bed 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -2235,12 +2235,16 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 reserved_at_440[0x8]; u8 max_num_eqs_24b[0x18]; =20 - u8 reserved_at_460[0x160]; + u8 reserved_at_460[0x144]; + u8 load_balance_id[0x4]; + u8 reserved_at_5a8[0x18]; =20 u8 query_adjacent_functions_id[0x1]; u8 ingress_egress_esw_vport_connect[0x1]; u8 function_id_type_vhca_id[0x1]; - u8 reserved_at_5c3[0xd]; + u8 reserved_at_5c3[0x1]; + u8 lag_per_mp_group[0x1]; + u8 reserved_at_5c5[0xb]; u8 delegate_vhca_management_profiles[0x10]; =20 u8 delegated_vhca_max[0x10]; --=20 2.31.1