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Tue, 16 Sep 2025 07:12:42 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jiri Pirko , Jonathan Corbet , "Leon Romanovsky" , Jason Gunthorpe , Saeed Mahameed , Tariq Toukan , Mark Bloch , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , "John Fastabend" , , , , , , Gal Pressman , Cosmin Ratiu , Dragos Tatulea , Jiri Pirko , Jason Gunthorpe Subject: [PATCH net-next V2 06/10] net/mlx5e: Prepare for using different CQ doorbells Date: Tue, 16 Sep 2025 17:11:40 +0300 Message-ID: <1758031904-634231-7-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758031904-634231-1-git-send-email-tariqt@nvidia.com> References: <1758031904-634231-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4C:EE_|BY5PR12MB4259:EE_ X-MS-Office365-Filtering-Correlation-Id: e7448fb1-bff5-4c1d-3240-08ddf52b261c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?gPUap6NCyZRbwItlVGYaRE3cccq7bmGz9+oNalguPVcF2RbbO0aOdleI2CvZ?= =?us-ascii?Q?d8IEGBEnhRPjcivR4kOczsYoh3jzOY7Jp3oAeAk2cdUjc2jH+MZYMY5zhQNS?= =?us-ascii?Q?iFwMLh/O4XZCX2v61qPdll46YgBrvjVvl9rLk+Dn8oWCat3Kewkj1arRIF8U?= =?us-ascii?Q?iZfvUfta7VbEym8WPssn99RoPWBOg0lffgvnNnaGc+KuvPRMug5cBMV8sNGy?= =?us-ascii?Q?RnS7o+b4BnIMR2WUF0dM4LpGaCVGxSpZZ2SZAwe1Pt4WvACiSEO4gXOKhpQT?= =?us-ascii?Q?xaqYJKz8ar70FLVdGyOfWBsb0OkUNNP0o+gnADc4MyIC+pNsv38ylQaaxRNz?= =?us-ascii?Q?7mBfFwMAyFEle9xlcNp0r7tkpUoSq7axW7kWhKVYG6/EmS5ExYJHMNmzgs3o?= =?us-ascii?Q?wprcxEV4IXeAMNbvyXeNN5GcuIiqs+UDnzzPQyJX+7i3vhGzNbvHW23jcn1H?= =?us-ascii?Q?yxg9+rQhRcZsP9ZeRek4BZm98twNkA3RpRC3uNv5nnWk+brgEMR4TqCAD90E?= =?us-ascii?Q?CtJTL2MKTWFpvfyV8lr4CPK04bp4TnRzlRSdPHicvWaFNUsd78e0/qaIoyZj?= =?us-ascii?Q?byn9ybwUhCOCLuefVspbaYms9Y1DpsXDlf1JtJvEWLPVtKRnt+t4qNzPx23Q?= =?us-ascii?Q?miAiowFX4Tcd40sb6zcgrA3F1S/RVV9B/BB55Unpx2i43qAr6TjliXI0Qnw8?= =?us-ascii?Q?KT46fFs0Duksh7J3swYH+7jhKolD0y9dlNcYNYpQvtLaYfXbV8zKCQIlZCcd?= =?us-ascii?Q?IgggMzIIcb+tCqxP8D7sU9L3vdeRmo3AFoC4GEol0AuOUh2g7rLNFQQXpF7j?= =?us-ascii?Q?V5G9lLhOo4365ckRijOuqQxblOoYGh8rTmNg53Kh3RLq3dQ1QEKTK0uNTgNA?= =?us-ascii?Q?y3G1dk02yJoouIp90+bippawr/HiMnQLds2gxlNtaaz/tTZU7dLb41TbJs4M?= =?us-ascii?Q?/duVVDs4zJo3jtTfhKe6Av8QftKcglz37cvF/O736euuCFoceEAxfXPk2XDW?= =?us-ascii?Q?ICA8UgZ3LQ5PXeJ4RGvO110hV06+qCCxk5EEdjDVgJkZ/uwdJcJvx1nQIbXo?= =?us-ascii?Q?UBWwBTJKKvliZtMcs5Z80NvPQXxpFYc4k1FSGQOcFgQMDQLBd4FXKBmPDh3u?= =?us-ascii?Q?EMeb8gIirtltlHwoSWUFIsfhJZafGIO/LVyEh75OKkiGe7m/WQN2qx51C2OE?= =?us-ascii?Q?dDF+yDuPD4hjIqS2EjTEFKEnfSYyByNEuAlWqy0Pq7JTOrc7VxqQozHk4CyF?= =?us-ascii?Q?EVLlwD7rpcYigwOqr0TzeA0KiVrBbPLa/AvhdPD8gsIQqLpPwabJHVLXY8i/?= =?us-ascii?Q?fZQiPR6o+Q7g4FPwp9Ha/bZEKoDBvckyL20XJd2wCuDbsKiMxnsOAzbxz9v8?= =?us-ascii?Q?sW1/5+VGX+chYpMUBsgXUBpRtOMiJCLv4lCDMyQItEXxE4tJ8ciCRNwO7Qc5?= =?us-ascii?Q?oxsbWEpWk9iwE5zWvtVGnhhd3IkdBJ+eX5PdLls+f0/BQkeln8KMvSsiz7XP?= =?us-ascii?Q?xla0aVMS7I6cH0j++c+RYGyyQni5jetfkNuy?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2025 14:13:02.6956 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7448fb1-bff5-4c1d-3240-08ddf52b261c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4259 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Completion queues (CQs) in mlx5 use the same global doorbell, which may become contended when accessed concurrently from many cores. This patch prepares the CQ management code for supporting different doorbells per CQ. This will be used in downstream patches to allow separate doorbells to be used by channels CQs. The main change is moving the 'uar' pointer from struct mlx5_core_cq to struct mlx5e_cq, as the uar page to be used is better off stored directly there. Other users of mlx5_core_cq also store the UAR to be used separately and therefore the pointer being removed is dead weight for them. As evidence, in this patch there are two users which set the mcq.uar pointer but didn't use it, Software Steering and old Innova CQ creation code. Instead, they rang the doorbell directly from another pointer. The 'uar' pointer added to struct mlx5e_cq remains in a hot cacheline (as before), because it may get accessed for each packet. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/cq.c | 1 - drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h | 5 +---- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 10 +++++++--- drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c | 1 - .../ethernet/mellanox/mlx5/core/steering/sws/dr_send.c | 1 - include/linux/mlx5/cq.h | 1 - 7 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cq.c b/drivers/net/eth= ernet/mellanox/mlx5/core/cq.c index 35039a95dcfd..e9f319a9bdd6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/cq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/cq.c @@ -145,7 +145,6 @@ int mlx5_create_cq(struct mlx5_core_dev *dev, struct ml= x5_core_cq *cq, mlx5_core_dbg(dev, "failed adding CP 0x%x to debug file system\n", cq->cqn); =20 - cq->uar =3D dev->priv.bfreg.up; cq->irqn =3D eq->core.irqn; =20 return 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 9c73165653bf..1cbe3f3037bb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -344,6 +344,7 @@ struct mlx5e_cq { /* data path - accessed per napi poll */ u16 event_ctr; struct napi_struct *napi; + struct mlx5_uars_page *uar; struct mlx5_core_cq mcq; struct mlx5e_ch_stats *ch_stats; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/en/txrx.h index 5dc04bbfc71b..6760bb0336df 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h @@ -309,10 +309,7 @@ mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, void _= _iomem *uar_map, =20 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) { - struct mlx5_core_cq *mcq; - - mcq =3D &cq->mcq; - mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); + mlx5_cq_arm(&cq->mcq, MLX5_CQ_DB_REQ_NOT, cq->uar->map, cq->wq.cc); } =20 static inline struct mlx5e_sq_dma * diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 0425f0e3d3a0..ef7598e048b2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -2185,6 +2185,7 @@ static void mlx5e_close_xdpredirect_sq(struct mlx5e_x= dpsq *xdpsq) static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev, struct net_device *netdev, struct workqueue_struct *workqueue, + struct mlx5_uars_page *uar, struct mlx5e_cq_param *param, struct mlx5e_cq *cq) { @@ -2216,6 +2217,7 @@ static int mlx5e_alloc_cq_common(struct mlx5_core_dev= *mdev, cq->mdev =3D mdev; cq->netdev =3D netdev; cq->workqueue =3D workqueue; + cq->uar =3D uar; =20 return 0; } @@ -2231,7 +2233,8 @@ static int mlx5e_alloc_cq(struct mlx5_core_dev *mdev, param->wq.db_numa_node =3D ccp->node; param->eq_ix =3D ccp->ix; =20 - err =3D mlx5e_alloc_cq_common(mdev, ccp->netdev, ccp->wq, param, cq); + err =3D mlx5e_alloc_cq_common(mdev, ccp->netdev, ccp->wq, + mdev->priv.bfreg.up, param, cq); =20 cq->napi =3D ccp->napi; cq->ch_stats =3D ccp->ch_stats; @@ -2276,7 +2279,7 @@ static int mlx5e_create_cq(struct mlx5e_cq *cq, struc= t mlx5e_cq_param *param) MLX5_SET(cqc, cqc, cq_period_mode, mlx5e_cq_period_mode(param->cq_period_= mode)); =20 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); - MLX5_SET(cqc, cqc, uar_page, mdev->priv.bfreg.up->index); + MLX5_SET(cqc, cqc, uar_page, cq->uar->index); MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); @@ -3589,7 +3592,8 @@ static int mlx5e_alloc_drop_cq(struct mlx5e_priv *pri= v, param->wq.buf_numa_node =3D dev_to_node(mlx5_core_dma_dev(mdev)); param->wq.db_numa_node =3D dev_to_node(mlx5_core_dma_dev(mdev)); =20 - return mlx5e_alloc_cq_common(priv->mdev, priv->netdev, priv->wq, param, c= q); + return mlx5e_alloc_cq_common(priv->mdev, priv->netdev, priv->wq, + mdev->priv.bfreg.up, param, cq); } =20 int mlx5e_open_drop_rq(struct mlx5e_priv *priv, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c b/drivers/= net/ethernet/mellanox/mlx5/core/fpga/conn.c index c4de6bf8d1b6..cb1319974f83 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c @@ -475,7 +475,6 @@ static int mlx5_fpga_conn_create_cq(struct mlx5_fpga_co= nn *conn, int cq_size) *conn->cq.mcq.arm_db =3D 0; conn->cq.mcq.vector =3D 0; conn->cq.mcq.comp =3D mlx5_fpga_conn_cq_complete; - conn->cq.mcq.uar =3D fdev->conn_res.uar; tasklet_setup(&conn->cq.tasklet, mlx5_fpga_conn_cq_tasklet); =20 mlx5_fpga_dbg(fdev, "Created CQ #0x%x\n", conn->cq.mcq.cqn); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c index 4fd4e8483382..077a77fde670 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c @@ -1131,7 +1131,6 @@ static struct mlx5dr_cq *dr_create_cq(struct mlx5_cor= e_dev *mdev, *cq->mcq.arm_db =3D cpu_to_be32(2 << 28); =20 cq->mcq.vector =3D 0; - cq->mcq.uar =3D uar; cq->mdev =3D mdev; =20 return cq; diff --git a/include/linux/mlx5/cq.h b/include/linux/mlx5/cq.h index 991526039ccb..7ef2c7c7d803 100644 --- a/include/linux/mlx5/cq.h +++ b/include/linux/mlx5/cq.h @@ -41,7 +41,6 @@ struct mlx5_core_cq { int cqe_sz; __be32 *set_ci_db; __be32 *arm_db; - struct mlx5_uars_page *uar; refcount_t refcount; struct completion free; unsigned vector; --=20 2.31.1