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Tue, 16 Sep 2025 07:12:35 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jiri Pirko , Jonathan Corbet , "Leon Romanovsky" , Jason Gunthorpe , Saeed Mahameed , Tariq Toukan , Mark Bloch , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , "John Fastabend" , , , , , , Gal Pressman , Cosmin Ratiu , Dragos Tatulea , Jiri Pirko , Jason Gunthorpe Subject: [PATCH net-next V2 05/10] net/mlx5e: Prepare for using multiple TX doorbells Date: Tue, 16 Sep 2025 17:11:39 +0300 Message-ID: <1758031904-634231-6-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758031904-634231-1-git-send-email-tariqt@nvidia.com> References: <1758031904-634231-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F67:EE_|SJ2PR12MB7865:EE_ X-MS-Office365-Filtering-Correlation-Id: ed2db74e-1bc0-425a-f4bd-08ddf52b247a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?8i4CdJ+ZxnjEXMtYrS3w8qkMiAmVrk1sP8VCBWEKy47oEd/U5+qAoPtLdXWb?= =?us-ascii?Q?tyJpiAnYGKbICpa8UBgqGgu0ddYSbgfgGPJXK423T+aV/4j0BdxsC1nqXusf?= =?us-ascii?Q?xM+dB7ok1TxaQkzbCY6dIL2ACAqVWb11QZAx4OWNbdzFZV1T+CWfM3l7lSA2?= =?us-ascii?Q?PFNoOBfcsJjdL+pDUmJhowXROPIV/WzjwN+ZZc/F1k7Q6dn8pPBhKMrjp8J8?= =?us-ascii?Q?ml41PveOBX2vGH40MXgrWL3gvwp/PPJ/OimJzWEu6qvPyq8CRzqKzMPxeEDJ?= =?us-ascii?Q?m2bATqwIjncG+ek3p3vDWRED12K9urnpCj2suFn7pam0s4n4OSP8yz6hreA1?= =?us-ascii?Q?giAFyTTa3jQc0QSMDZtD2MuKkpabn7dy4LJwS8CB34mjt2m6bxTeqcbK13pX?= =?us-ascii?Q?9P7dJvE4vYUbk1ymPkG/sxvqfrCbbe7cYqPXr9wa9uUkMvuQ1iaEgY+xmZDA?= =?us-ascii?Q?+G800ka34G4sYB1jbmG1sYxE53HcDfOFo9RHWd2coL/g94QmCnyuUmEooAs/?= =?us-ascii?Q?WyniiuXMQr/UWc/Gswy7iIzcG+AxRfFkW5wzEqQykog3LrPoiHa9NsPUeN04?= =?us-ascii?Q?1RFyAVOrVs70fjj/Zz7m78VQLV1HJYQvD1lNhiLTB/NV1/nDpO1gbp0DOUqp?= =?us-ascii?Q?+nSyNJpmmbNgBJObHJcnIfqeIDNn0OobjsaMRMN0rqtKqQ+zzbS08Yuu6Ie/?= =?us-ascii?Q?vto193cyQvSp3Ot408u1PkGnFKgZmlbY+E9cgTAFV/yCjf3qv+9ftuM30K8p?= =?us-ascii?Q?TCKqke2FurzF8mexOJq1wdBMhUzHuinWSdUYD+4IDubWSEM718aWXwoZI858?= =?us-ascii?Q?HfFjA2LBBd4aIrdeRbIlS3PWyfWytdTe0ZrRQjcOlpk/voFAJlr03XqRv/G2?= =?us-ascii?Q?J45XVqu67a3AAEbWInAdSUGa5sb1iSL/ZFC4rzzbp2M/TiGrJbdeS9wIPnhg?= =?us-ascii?Q?zkbxpylCkTNcH01KyDHxNnRedUfKHDVLo/NX9I+dug8kWvdTE6vfSyeSBOOK?= =?us-ascii?Q?O9bOFRCCXRfiT0VcEk6SeEnTZJj1PvfZC733eXuPh1sWfINBw/bcCzKagij3?= =?us-ascii?Q?xvfA4oxSvNso6bctBWRH2yF92y4Pbcv+EMyZ09R2vYRGnkrOZRRYqM/W0aNd?= =?us-ascii?Q?iUZW0BrvxM/7dnl8fNcfkOvxWVA+EzcZO8H+7z57a3vsepv+o9QVFfrzgYIB?= =?us-ascii?Q?qnxERt51qwo60ENBLyjXxWU71JNp5UEg+jHNMN9AL9T4sPr7FWbCt6yUM+8X?= =?us-ascii?Q?mnKMmcAUHXratpa89jTd+Jfo00tT9+4qo7/b6a6bdMTIrE7N62ChdKRBqR1q?= =?us-ascii?Q?oT34ganbxD7vWNWl7w+/X7yGaMkDhlCHMdzEwOBxdc4TivMCuYvnGTYZ4ond?= =?us-ascii?Q?TIj4/deyMg98v4Tm/ZFPZH99uTUtnS2adxpWDsMq11Bq3SSZCjjHNuoKvMip?= =?us-ascii?Q?hLjuBAqKsJHbHX+0cC1ssJdJI5y1YqVXyChCr2cm33NWk9x/jPiKVefi17JP?= =?us-ascii?Q?pW3P06QDmyLW1ZIhbi1VI/Vf2PuuCAim8WAq?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2025 14:12:59.9345 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed2db74e-1bc0-425a-f4bd-08ddf52b247a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F67.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7865 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu The driver allocates a single doorbell per device and uses it for all Send Queues (SQs). This can become a bottleneck due to the high number of concurrent MMIO accesses when ringing the same doorbell from many channels. This patch makes the doorbells used by channel queues configurable. mlx5e_channel_pick_doorbell() is added to select the doorbell to be used for a given channel, picking the default for now. When opening a channel, the selected doorbell is saved to the channel struct and used whenever channel-related queues are created. Finally, 'uar_page' is added to 'struct mlx5e_create_sq_param' to control which doorbell to use when allocating an SQ, since that can happen outside channel context (e.g. for PTP). Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + .../ethernet/mellanox/mlx5/core/en/params.h | 1 + .../net/ethernet/mellanox/mlx5/core/en/ptp.c | 4 +++- .../net/ethernet/mellanox/mlx5/core/en/ptp.h | 1 + .../net/ethernet/mellanox/mlx5/core/en_main.c | 18 ++++++++++++++---- 5 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 0dd3bc0f4caa..9c73165653bf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -788,6 +788,7 @@ struct mlx5e_channel { int vec_ix; int sd_ix; int cpu; + struct mlx5_sq_bfreg *bfreg; /* Sync between icosq recovery and XSK enable/disable. */ struct mutex icosq_recovery_lock; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.h index e3edf79dde5f..00617c65fe3c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h @@ -51,6 +51,7 @@ struct mlx5e_create_sq_param { u32 tisn; u8 tis_lst_sz; u8 min_inline_mode; + u32 uar_page; }; =20 /* Striding RQ dynamic parameters */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/ptp.c index 7c1d9a9ea464..a392578a063c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c @@ -334,7 +334,7 @@ static int mlx5e_ptp_alloc_txqsq(struct mlx5e_ptp *c, i= nt txq_ix, sq->mdev =3D mdev; sq->ch_ix =3D MLX5E_PTP_CHANNEL_IX; sq->txq_ix =3D txq_ix; - sq->uar_map =3D mdev->priv.bfreg.map; + sq->uar_map =3D c->bfreg->map; sq->min_inline_mode =3D params->tx_min_inline_mode; sq->hw_mtu =3D MLX5E_SW2HW_MTU(params, params->sw_mtu); sq->stats =3D &c->priv->ptp_stats.sq[tc]; @@ -486,6 +486,7 @@ static int mlx5e_ptp_open_txqsq(struct mlx5e_ptp *c, u3= 2 tisn, csp.wq_ctrl =3D &txqsq->wq_ctrl; csp.min_inline_mode =3D txqsq->min_inline_mode; csp.ts_cqe_to_dest_cqn =3D ptpsq->ts_cq.mcq.cqn; + csp.uar_page =3D c->bfreg->index; =20 err =3D mlx5e_create_sq_rdy(c->mdev, sqp, &csp, 0, &txqsq->sqn); if (err) @@ -900,6 +901,7 @@ int mlx5e_ptp_open(struct mlx5e_priv *priv, struct mlx5= e_params *params, c->num_tc =3D mlx5e_get_dcb_num_tc(params); c->stats =3D &priv->ptp_stats.ch; c->lag_port =3D lag_port; + c->bfreg =3D &mdev->priv.bfreg; =20 err =3D mlx5e_ptp_set_state(c, params); if (err) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/ptp.h index 883c044852f1..1b3c9648220b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h @@ -66,6 +66,7 @@ struct mlx5e_ptp { struct mlx5_core_dev *mdev; struct hwtstamp_config *tstamp; DECLARE_BITMAP(state, MLX5E_PTP_STATE_NUM_STATES); + struct mlx5_sq_bfreg *bfreg; }; =20 static inline bool mlx5e_use_ptpsq(struct sk_buff *skb) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 02a538ec2ecb..0425f0e3d3a0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -1532,7 +1532,7 @@ static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, sq->pdev =3D c->pdev; sq->mkey_be =3D c->mkey_be; sq->channel =3D c; - sq->uar_map =3D mdev->priv.bfreg.map; + sq->uar_map =3D c->bfreg->map; sq->min_inline_mode =3D params->tx_min_inline_mode; sq->hw_mtu =3D MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN; sq->xsk_pool =3D xsk_pool; @@ -1617,7 +1617,7 @@ static int mlx5e_alloc_icosq(struct mlx5e_channel *c, int err; =20 sq->channel =3D c; - sq->uar_map =3D mdev->priv.bfreg.map; + sq->uar_map =3D c->bfreg->map; sq->reserved_room =3D param->stop_room; =20 param->wq.db_numa_node =3D cpu_to_node(c->cpu); @@ -1702,7 +1702,7 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, sq->priv =3D c->priv; sq->ch_ix =3D c->ix; sq->txq_ix =3D txq_ix; - sq->uar_map =3D mdev->priv.bfreg.map; + sq->uar_map =3D c->bfreg->map; sq->min_inline_mode =3D params->tx_min_inline_mode; sq->hw_mtu =3D MLX5E_SW2HW_MTU(params, params->sw_mtu); sq->max_sq_mpw_wqebbs =3D mlx5e_get_max_sq_aligned_wqebbs(mdev); @@ -1778,7 +1778,7 @@ static int mlx5e_create_sq(struct mlx5_core_dev *mdev, MLX5_SET(sqc, sqc, flush_in_error_en, 1); =20 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); - MLX5_SET(wq, wq, uar_page, mdev->priv.bfreg.index); + MLX5_SET(wq, wq, uar_page, csp->uar_page); MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma); @@ -1882,6 +1882,7 @@ int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tis= n, int txq_ix, csp.cqn =3D sq->cq.mcq.cqn; csp.wq_ctrl =3D &sq->wq_ctrl; csp.min_inline_mode =3D sq->min_inline_mode; + csp.uar_page =3D c->bfreg->index; err =3D mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq= ->sqn); if (err) goto err_free_txqsq; @@ -2052,6 +2053,7 @@ static int mlx5e_open_icosq(struct mlx5e_channel *c, = struct mlx5e_params *params csp.cqn =3D sq->cq.mcq.cqn; csp.wq_ctrl =3D &sq->wq_ctrl; csp.min_inline_mode =3D params->tx_min_inline_mode; + csp.uar_page =3D c->bfreg->index; err =3D mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); if (err) goto err_free_icosq; @@ -2112,6 +2114,7 @@ int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct = mlx5e_params *params, csp.cqn =3D sq->cq.mcq.cqn; csp.wq_ctrl =3D &sq->wq_ctrl; csp.min_inline_mode =3D sq->min_inline_mode; + csp.uar_page =3D c->bfreg->index; set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); =20 err =3D mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); @@ -2740,6 +2743,11 @@ void mlx5e_trigger_napi_sched(struct napi_struct *na= pi) local_bh_enable(); } =20 +static void mlx5e_channel_pick_doorbell(struct mlx5e_channel *c) +{ + c->bfreg =3D &c->mdev->priv.bfreg; +} + static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, struct mlx5e_params *params, struct xsk_buff_pool *xsk_pool, @@ -2794,6 +2802,8 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv= , int ix, c->aff_mask =3D irq_get_effective_affinity_mask(irq); c->lag_port =3D mlx5e_enumerate_lag_port(mdev, ix); =20 + mlx5e_channel_pick_doorbell(c); + netif_napi_add_config_locked(netdev, &c->napi, mlx5e_napi_poll, ix); netif_napi_set_irq_locked(&c->napi, irq); =20 --=20 2.31.1