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Tue, 16 Sep 2025 07:12:16 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jiri Pirko , Jonathan Corbet , "Leon Romanovsky" , Jason Gunthorpe , Saeed Mahameed , Tariq Toukan , Mark Bloch , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , "John Fastabend" , , , , , , Gal Pressman , Cosmin Ratiu , Dragos Tatulea , Jiri Pirko , Jason Gunthorpe Subject: [PATCH net-next V2 02/10] net/mlx5: Remove unused 'offset' field from mlx5_sq_bfreg Date: Tue, 16 Sep 2025 17:11:36 +0300 Message-ID: <1758031904-634231-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758031904-634231-1-git-send-email-tariqt@nvidia.com> References: <1758031904-634231-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4E:EE_|CH1PR12MB9576:EE_ X-MS-Office365-Filtering-Correlation-Id: 72319b14-f607-4613-e109-08ddf52b19ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?rcxNf+d+W2crS174OVZ57ppIGslOm1GzuaHuqX5v9VOiT6k9hDcjL+qwUd+y?= =?us-ascii?Q?b0ZLBx854C53y5/Av3C46k/DKinAC4Yf5Gr/eky5SJQlgUydHI8hG6CpnLsl?= =?us-ascii?Q?Q1tjjq5jRJNe3jBjV9VupPiEHnrbj12FNZhNWixfFSQB8cuNfLYgOuuwMhUa?= =?us-ascii?Q?LhBRHu0LSRk6ntXIyEpPyyN7Kt/VkOPSMhF/BeV6L9dkAssSAmP/EbtL1pcj?= =?us-ascii?Q?1V6+ph4pFwoy/OdJTr3Qx1Gq7fVX5hCT3qZy2Ed/Khm8xZsUvcmdgbatE48L?= =?us-ascii?Q?Q+hlNOCDpcVoxvmwTJN12AbyLnce96wK9qwf0S8n7OX/dKREtZBtMoBVtoG1?= =?us-ascii?Q?Jqy0D2R/aJwkGYaEy8mXG2rKvI7AFaWyXlycFleHh4LOZakzpK7zOKsOm8Qn?= =?us-ascii?Q?UHdFTnmJirtskjikLK9D/yuqEAJ88j42N6KSMuXXMyuG/hYX4ul2EyBo1vJx?= =?us-ascii?Q?ngAirmVST15mL90FWr8SnxfafMhi39rx6aqmRF8lHxKtwmX6RxaVA5EZ9lrM?= =?us-ascii?Q?2f964usmQ1/nXrCRgf6v9ZZFHKI9Rcz1n2qe4xI1cEP6cksAFm6pvbrlbgZV?= =?us-ascii?Q?iXC9z553/UTKgJvBXudBKSyKhJUViGLr2TT6op5MYuJV0H0LmTOuqDhQbnG/?= =?us-ascii?Q?Sqf2DTw/r6eoWgDosESgZGguGtZhDA839l+geX28N5N7crtj3Gn1/KUjiOU6?= =?us-ascii?Q?gVzHW1QdA5cJrH2Ui1+vLmbeRoI3kzAq06ZBnsTo3QqQGyUpLMGbPnh5DG17?= =?us-ascii?Q?SqltptqJ+VYFMIMcofBGWUi4d0NpgF/FpDHcNW8H02mrEXKvhK9ZnpG+SX5G?= =?us-ascii?Q?QylU776SYBDqhi1TpD4O4yEAw/FrRdpaqQEHIdNTb1vXjU8bFIGdAG4Gu5Cg?= =?us-ascii?Q?7V8H7cKN0+DQzuTeIAm2++55CNB4SPlDHeQBZV1GtS3MRVeyc4UNz3OO6FLr?= =?us-ascii?Q?Q7PMuiXy+IFhfwRxEF3270DQ1CgxJsjbpdWUEtAhoRTwrctMK8w9vUPMFfyO?= =?us-ascii?Q?97mU2h2oOdr5oOYnYf8pfmgpU+X2ffemigtcZrwh2fH1rILcQS7zRbC44iYL?= =?us-ascii?Q?TE69UUDj1MvEwYhauqm9T765d1PtcNjjLBtjke/MKDwqxsRmKXd+smlIedms?= =?us-ascii?Q?J/lfUT9QRHANoumbc6cu+mqkZMHlmx3X6jg2IC7KrjW9yJSgDQqXPXcGGswG?= =?us-ascii?Q?QRVwgL8our8g2i9nAKm+DcphRTEzBV07qlSHBfvEK4e39N1lYvY+1i/PYptu?= =?us-ascii?Q?T8ygx6xCf2rQeKaDkeHvFvgKTKA/q0+2VfXW2fodEunAAHO+wReH885ZLjy5?= =?us-ascii?Q?2Cq2xVUuGo/yBpLiOAbUZpxk20qhAhJaq8+GnrvcxrmlEEejVrhTvXYtQGWU?= =?us-ascii?Q?KzxNimvOG2vFuLllIrGvwpzOvxEpKgdrr2Dl/s3XIWjLRMevmf5G39PptJzT?= =?us-ascii?Q?iIwkuZdcdytXXKzZIVDmZiAPYaNAzOlMQ9TSsN20KFlLtmnRbtgBXF8ZXYfr?= =?us-ascii?Q?fedwOmAwW3pGlDgpR/I4qc4FnSIMYr+vkrlw?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2025 14:12:42.2133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 72319b14-f607-4613-e109-08ddf52b19ea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9576 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu The 'offset' field was introduced in the original commit [1] and never used until commit [2], which added an unnecessary use. Remove the field and refactor the write-combining test to use a local variable instead. [1] commit a6d51b68611e ("net/mlx5: Introduce blue flame register allocator") [2] commit d98995b4bf98 ("net/mlx5: Reimplement write combining test") Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/wc.c | 12 +++++++----- include/linux/mlx5/driver.h | 1 - 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/wc.c b/drivers/net/eth= ernet/mellanox/mlx5/core/wc.c index 2f0316616fa4..276594586404 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/wc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/wc.c @@ -255,7 +255,8 @@ static void mlx5_wc_destroy_sq(struct mlx5_wc_sq *sq) mlx5_wq_destroy(&sq->wq_ctrl); } =20 -static void mlx5_wc_post_nop(struct mlx5_wc_sq *sq, bool signaled) +static void mlx5_wc_post_nop(struct mlx5_wc_sq *sq, unsigned int *offset, + bool signaled) { int buf_size =3D (1 << MLX5_CAP_GEN(sq->cq.mdev, log_bf_reg_size)) / 2; struct mlx5_wqe_ctrl_seg *ctrl; @@ -288,10 +289,10 @@ static void mlx5_wc_post_nop(struct mlx5_wc_sq *sq, b= ool signaled) */ wmb(); =20 - __iowrite64_copy(sq->bfreg.map + sq->bfreg.offset, mmio_wqe, + __iowrite64_copy(sq->bfreg.map + *offset, mmio_wqe, sizeof(mmio_wqe) / 8); =20 - sq->bfreg.offset ^=3D buf_size; + *offset ^=3D buf_size; } =20 static int mlx5_wc_poll_cq(struct mlx5_wc_sq *sq) @@ -332,6 +333,7 @@ static int mlx5_wc_poll_cq(struct mlx5_wc_sq *sq) =20 static void mlx5_core_test_wc(struct mlx5_core_dev *mdev) { + unsigned int offset =3D 0; unsigned long expires; struct mlx5_wc_sq *sq; int i, err; @@ -358,9 +360,9 @@ static void mlx5_core_test_wc(struct mlx5_core_dev *mde= v) goto err_create_sq; =20 for (i =3D 0; i < TEST_WC_NUM_WQES - 1; i++) - mlx5_wc_post_nop(sq, false); + mlx5_wc_post_nop(sq, &offset, false); =20 - mlx5_wc_post_nop(sq, true); + mlx5_wc_post_nop(sq, &offset, true); =20 expires =3D jiffies + TEST_WC_POLLING_MAX_TIME_JIFFIES; do { diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index fcfc18bfeba9..5a85b6d91ba3 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -434,7 +434,6 @@ struct mlx5_sq_bfreg { struct mlx5_uars_page *up; bool wc; u32 index; - unsigned int offset; }; =20 struct mlx5_core_health { --=20 2.31.1