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Mon, 15 Sep 2025 05:25:21 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Jianbo Liu Subject: [PATCH net V2 1/3] net/mlx5e: Harden uplink netdev access against device unbind Date: Mon, 15 Sep 2025 15:24:32 +0300 Message-ID: <1757939074-617281-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1757939074-617281-1-git-send-email-tariqt@nvidia.com> References: <1757939074-617281-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD2:EE_|MN2PR12MB4222:EE_ X-MS-Office365-Filtering-Correlation-Id: 71bda616-7180-4575-b4f9-08ddf452fcd5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?OkQysaOORFp1aHQaft51usDqLcMpLmrYIUCoIFuI8GPVCKo7UzSuS5un2UsE?= =?us-ascii?Q?6mgmqzCPnbjCGueNh63vLl13WI4gCCTgk4P57sFWobiA7V6EMpVOGCBF+QGZ?= =?us-ascii?Q?iNItfFQAKAiLUHvegWUybx8irW8TWwBArW/BDNFtxmYOo5INKVgaj72ruG8S?= =?us-ascii?Q?pTvb758VljJoGJGEtwTdsM2J3ffQXcHqBqwCl5IP0HkDAjo/RNhbE8IW7XN1?= =?us-ascii?Q?Lo3fPlgrlnI8LwHiK/37RJ5yrF8SHgLAf4vfUptga0pzBJRQgq3Jfx4Arjla?= =?us-ascii?Q?//m+xQ7oh5aZMCw9udKCR5TbqrkNsb7igoC3F1b6lB1jWSdGHqTVPJhLj53q?= =?us-ascii?Q?KL4HeJYTQ/d9EJm8N2r9LctW6WzT9mDg693k2bCHIix2vvVfSpA6eWbH7Q8V?= =?us-ascii?Q?5yyNgL0xFgiGfO3NJSVRiwKOxKw2v83qQ4nrCZ+BD6EUbBmhD7n/j3HS2Vw6?= =?us-ascii?Q?23xMnKK/haZ9aYiOze9PwmZ8Ik+mEnunA1UOD5hOu9GmV3WNed0IAE5ptFjJ?= =?us-ascii?Q?xsU7WSm2Snjz51+fSWBFkwayo5dw7LGmE9eIoNCpO+1J3CUyKKVFRQw5xG8C?= =?us-ascii?Q?rg0kaHNfJvnueeAj8N2nbUDO/yTZHlHZFcfz/U6aEZiZWu9HBhjS6cIabI9o?= =?us-ascii?Q?sseQ4eierXHPjkoCrvxC5XPywJudCejEYYJknnZlf86oA7N6EWvcGcTGLP7q?= =?us-ascii?Q?j0NFOmm4yudT+/N4DbwbgwAQ5Ulv9NcD1CnC7ij0qVobUhAyUmmaxrcREp+U?= =?us-ascii?Q?gHgiOB3FpWeUaEruJ/a4STj/91TjuOrK+Gcsbbd1bbUloyf+SDC/U+6kiqe7?= =?us-ascii?Q?/1x27XSkGPrNB4LTzoUzLSlxkwb6e9SN6ORgIZCWpWttkQP/Yb+T8kVOiitP?= =?us-ascii?Q?/1eyR4u80lBw0Q3bLTguWb9ef7b7DjL0Cou4vgyB5Y0OLpFHFtUJ/Msat/Xj?= =?us-ascii?Q?8P3/glFQN2QbIccvUi85T4sVKNaLjvfPGSMLAVrl80vsB20ulKPWkojK/eyU?= =?us-ascii?Q?iu3Bf3ePDm81htNAVdJax2Hz/pSVGZdEEKAumF3XHjDjQwGF48Bs5sMn1yhR?= =?us-ascii?Q?9TKG43BiJIjGBxmDmnyslb5ilvRkJPzZ7yn4+OhVnoBEg+d5dDYpt7ZCgoxN?= =?us-ascii?Q?k2a1c2YL/PA8H1SO3ZQcVneL2foSp4bqxxub9j3SfXUrO8oynrpk6UYB4Bvh?= =?us-ascii?Q?6u6Pt36cO7bTLL6CK5k+F0W8l5k1SXrZZ/kXXT0UlzkS2iM+b+DbpsXBXAXv?= =?us-ascii?Q?VjJvr3RZdBGeMPNCr+iT6wfShH9etDONc47FHUM2t3OFt+kqr7gCw+ykCS8P?= =?us-ascii?Q?a01YI459DvJ2ZnX1+b9EusmbPhjnIwhQSlZ4ydzoAJdHczcuQ7CRLeL0e00C?= =?us-ascii?Q?pcymR1hPbJU6yr0+cc8X5Y0XGt+C5WMdmP/AFcyT/dkNfwMA/2sCtaDl/O3A?= =?us-ascii?Q?Vgw81yXvD0rh1P7wra2+FnTB/DPpfQ78VJ4xj62UMvt9ijCIw8hZuBozXAz/?= =?us-ascii?Q?W39iQl8IT4DOWE3nMRK6Rg+5nzW7vQzvRqDF?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2025 12:25:42.1635 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71bda616-7180-4575-b4f9-08ddf452fcd5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4222 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jianbo Liu The function mlx5_uplink_netdev_get() gets the uplink netdevice pointer from mdev->mlx5e_res.uplink_netdev. However, the netdevice can be removed and its pointer cleared when unbound from the mlx5_core.eth driver. This results in a NULL pointer, causing a kernel panic. BUG: unable to handle page fault for address: 0000000000001300 at RIP: 0010:mlx5e_vport_rep_load+0x22a/0x270 [mlx5_core] Call Trace: mlx5_esw_offloads_rep_load+0x68/0xe0 [mlx5_core] esw_offloads_enable+0x593/0x910 [mlx5_core] mlx5_eswitch_enable_locked+0x341/0x420 [mlx5_core] mlx5_devlink_eswitch_mode_set+0x17e/0x3a0 [mlx5_core] devlink_nl_eswitch_set_doit+0x60/0xd0 genl_family_rcv_msg_doit+0xe0/0x130 genl_rcv_msg+0x183/0x290 netlink_rcv_skb+0x4b/0xf0 genl_rcv+0x24/0x40 netlink_unicast+0x255/0x380 netlink_sendmsg+0x1f3/0x420 __sock_sendmsg+0x38/0x60 __sys_sendto+0x119/0x180 do_syscall_64+0x53/0x1d0 entry_SYSCALL_64_after_hwframe+0x4b/0x53 Ensure the pointer is valid before use by checking it for NULL. If it is valid, immediately call netdev_hold() to take a reference, and preventing the netdevice from being freed while it is in use. Fixes: 7a9fb35e8c3a ("net/mlx5e: Do not reload ethernet ports when changing= eswitch mode") Signed-off-by: Jianbo Liu Reviewed-by: Cosmin Ratiu Reviewed-by: Jiri Pirko Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_rep.c | 27 +++++++++++++++---- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 1 + .../ethernet/mellanox/mlx5/core/lib/mlx5.h | 15 ++++++++++- include/linux/mlx5/driver.h | 1 + 4 files changed, 38 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c b/drivers/net= /ethernet/mellanox/mlx5/core/en_rep.c index 63a7a788fb0d..cd0242eb008c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c @@ -1506,12 +1506,21 @@ static const struct mlx5e_profile mlx5e_uplink_rep_= profile =3D { static int mlx5e_vport_uplink_rep_load(struct mlx5_core_dev *dev, struct mlx5_eswitch= _rep *rep) { - struct mlx5e_priv *priv =3D netdev_priv(mlx5_uplink_netdev_get(dev)); struct mlx5e_rep_priv *rpriv =3D mlx5e_rep_to_rep_priv(rep); + struct net_device *netdev; + struct mlx5e_priv *priv; + int err; + + netdev =3D mlx5_uplink_netdev_get(dev); + if (!netdev) + return 0; =20 + priv =3D netdev_priv(netdev); rpriv->netdev =3D priv->netdev; - return mlx5e_netdev_change_profile(priv, &mlx5e_uplink_rep_profile, - rpriv); + err =3D mlx5e_netdev_change_profile(priv, &mlx5e_uplink_rep_profile, + rpriv); + mlx5_uplink_netdev_put(dev, netdev); + return err; } =20 static void @@ -1638,8 +1647,16 @@ mlx5e_vport_rep_unload(struct mlx5_eswitch_rep *rep) { struct mlx5e_rep_priv *rpriv =3D mlx5e_rep_to_rep_priv(rep); struct net_device *netdev =3D rpriv->netdev; - struct mlx5e_priv *priv =3D netdev_priv(netdev); - void *ppriv =3D priv->ppriv; + struct mlx5e_priv *priv; + void *ppriv; + + if (!netdev) { + ppriv =3D rpriv; + goto free_ppriv; + } + + priv =3D netdev_priv(netdev); + ppriv =3D priv->ppriv; =20 if (rep->vport =3D=3D MLX5_VPORT_UPLINK) { mlx5e_vport_uplink_rep_unload(rpriv); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index 8b4977650183..5f2d6c35f1ad 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -1515,6 +1515,7 @@ static u32 mlx5_esw_qos_lag_link_speed_get_locked(str= uct mlx5_core_dev *mdev) speed =3D lksettings.base.speed; =20 out: + mlx5_uplink_netdev_put(mdev, slave); return speed; } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/mlx5.h b/drivers/n= et/ethernet/mellanox/mlx5/core/lib/mlx5.h index b111ccd03b02..74ea5da58b7e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/mlx5.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/mlx5.h @@ -47,7 +47,20 @@ int mlx5_crdump_collect(struct mlx5_core_dev *dev, u32 *= cr_data); =20 static inline struct net_device *mlx5_uplink_netdev_get(struct mlx5_core_d= ev *mdev) { - return mdev->mlx5e_res.uplink_netdev; + struct mlx5e_resources *mlx5e_res =3D &mdev->mlx5e_res; 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All other representors (VFs, SFs) are created in the netns of the devlink instance. If the PF's netns has been moved and differs from the devlink's netns, enabling switchdev mode would create a state where the OVS control plane (ovs-vsctl) cannot manage the switch because the PF uplink representor and the other representors are split across different namespaces. To prevent this inconsistent configuration, block the request to enter switchdev mode if the PF netdevice's netns does not match the netns of its devlink instance. As part of this change, the PF's netns is first marked as immutable. This prevents race conditions where the netns could be changed after the check is performed but before the mode transition is complete, and it aligns the PF's behavior with that of the final uplink representor. Fixes: 71c6eaebf06a ("net/mlx5e: Set netdev name space on creation") Signed-off-by: Jianbo Liu Reviewed-by: Cosmin Ratiu Reviewed-by: Jiri Pirko Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/eswitch_offloads.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index bee906661282..b204ed459760 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3739,6 +3739,29 @@ void mlx5_eswitch_unblock_mode(struct mlx5_core_dev = *dev) up_write(&esw->mode_lock); } =20 +/* Returns false only when uplink netdev exists and its netns is different= from + * devlink's netns. True for all others so entering switchdev mode is allo= wed. + */ +static bool mlx5_devlink_netdev_netns_immutable_set(struct devlink *devlin= k, + bool immutable) +{ + struct mlx5_core_dev *mdev =3D devlink_priv(devlink); + struct net_device *netdev; + bool ret; + + netdev =3D mlx5_uplink_netdev_get(mdev); + if (!netdev) + return true; + + rtnl_lock(); + netdev->netns_immutable =3D immutable; + ret =3D net_eq(dev_net(netdev), devlink_net(devlink)); + rtnl_unlock(); + + mlx5_uplink_netdev_put(mdev, netdev); + return ret; +} + int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, struct netlink_ext_ack *extack) { @@ -3781,6 +3804,14 @@ int mlx5_devlink_eswitch_mode_set(struct devlink *de= vlink, u16 mode, esw->eswitch_operation_in_progress =3D true; up_write(&esw->mode_lock); =20 + if (mode =3D=3D DEVLINK_ESWITCH_MODE_SWITCHDEV && + !mlx5_devlink_netdev_netns_immutable_set(devlink, true)) { + NL_SET_ERR_MSG_MOD(extack, + "Can't change E-Switch mode to switchdev when netdev net namespace = has diverged from the devlink's."); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Lama Kayal , Jianbo Liu , Chris Mi Subject: [PATCH net V2 3/3] net/mlx5e: Add a miss level for ipsec crypto offload Date: Mon, 15 Sep 2025 15:24:34 +0300 Message-ID: <1757939074-617281-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1757939074-617281-1-git-send-email-tariqt@nvidia.com> References: <1757939074-617281-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD3:EE_|DS0PR12MB8453:EE_ X-MS-Office365-Filtering-Correlation-Id: 7fd2c0f4-00b9-46ae-c62c-08ddf453001e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?01SclVeqnEoIspWzNc+rSUopnWCMNyrW6PKzoOJD1YIoXcP5J4IQ9hBhS647?= =?us-ascii?Q?6vialaXgFJ/VEQ2ETg8P8SZISsTNHVoFu/S9B/0Z5zjR4bML2FPBs3uXSmKW?= =?us-ascii?Q?vgklgHx1wlfJl6fq7b3bvrPAWGs7PtjS7hZKVcefrjl728vB2qchJt2MRL4n?= =?us-ascii?Q?U2NwzF1wNGPRcq+L19IsJleN9IvO+jESEVEbw6IbZTp7SMC4dmRBBDpTqm4A?= =?us-ascii?Q?dZDMzANcj8zSl/QsJGQfFOrVgUKYTHxa2i8zR4gKN5fpMnamG7hTHPNlpudE?= =?us-ascii?Q?6Lu1DzfltTN2Xs2mOwdJFyniQNQuPCpdh3Gk1bYPCYsAu6WAdfBQY02FiQB4?= =?us-ascii?Q?WA9fxlzv72bLg3joYQ5KDrsmlyNUqL8EIANhxzfITwm+HOkaJBKV2oLJTjl/?= =?us-ascii?Q?TYChNNw8bULUqnMY9GITABzToLD6peL9a82JqjKDxAhNO2ztX6C+bkK0OsJC?= =?us-ascii?Q?mx5i+AkeYR1nEk0k51lwX4D6MvTGAVUY+PRj2e2dvjC0ywuff1T0xJpax2CF?= =?us-ascii?Q?YShm3IlgtKQfSjPBNZ3dwnPAI6BUFBilO9H90hSSsLgjAC26mC/nNC1KrYpy?= =?us-ascii?Q?j2wGS5xPMjOKvOdFxg9eKxojZsfH0zkwqS94+mCwN0iSiM/kllfhdhu2kZSj?= =?us-ascii?Q?kZNQa+65obeSe0Ulk1Rmn74Li1YG7WPebSqLbASb6OJtQOnKTZEWmdKmkIux?= =?us-ascii?Q?qxj13uJAy+dS7OZ91MrhgRrQUeWhTBTHdQBoAODHK0CHfFTTgbu/ykfAPVJi?= =?us-ascii?Q?/Udrkltz4qYYlq3aWMBMHC05nEbXe6/yavu3BWQJ8LNMeGC7IQDVLQj8nXFM?= =?us-ascii?Q?97ASdl7k7dTYxE1tnOKk/inh5W2fLHA+mSaSo+2+pSzFEP2WZ1yO1jnJvgjT?= =?us-ascii?Q?us9ESQ2gYqxG7JxFcK0qq4JV167B80I9ByC3gdYkaEcSUnJNQ4fRyWtGxYDI?= =?us-ascii?Q?iIr0rpDrrqfqx2CLnbKLCnklK1MqG9rEZeWmCt2E4LXbTcICPJJBswoPYY0g?= =?us-ascii?Q?Yl3QKQjVFx+E9RtZ8B9YJGsv8pXowzbr94ECiMm6B4btae7gUT5wAoFQBbD8?= =?us-ascii?Q?Ykt3ydgk55R5O+uTWs43H5opN+9HOzpjtBK13Op1m5v3R7FPdSAVinp6J/bS?= =?us-ascii?Q?d8quNVPTJ0CibnNMnMGVEYE5vyWLyYjer81AE9P1DDBevPVNqWxAI2BhzW9Y?= =?us-ascii?Q?bJzOnBlfb+DGrhn65kIAWCeGewL1vvcU+jctFp8VpRVeS/+jVZhOBkDuPWUM?= =?us-ascii?Q?f5yhS/aIxgkHPo+oUmm/UiVLrj5vcmcqN+1sEAmldYsci6D7ynoQle8LV42K?= =?us-ascii?Q?Uu5MF2QWo9eva8H4AccHFyVNXNExUHMSjao95U+BpDhmHzc1YG/Ba3unCO31?= =?us-ascii?Q?wvumAP579XIOt2+R9srNfD/Di05t+T6qHkZITg5L4mgFgimknrL6uV9SPSkR?= =?us-ascii?Q?GxH8kmesOY+ItFLJ7C5D63LCY+j8OH3PPt1vy8pwe4gfKN7shTy4Gwmem6xE?= =?us-ascii?Q?eNCCklhYhlBrojcT/4lE1aj4TbG2YmeZYxNz?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2025 12:25:47.7365 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7fd2c0f4-00b9-46ae-c62c-08ddf453001e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8453 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lama Kayal The cited commit adds a miss table for switchdev mode. But it uses the same level as policy table. Will hit the following error when running command: # ip xfrm state add src 192.168.1.22 dst 192.168.1.21 proto \ esp spi 1001 reqid 10001 aead 'rfc4106(gcm(aes))' \ 0x3a189a7f9374955d3817886c8587f1da3df387ff 128 \ mode tunnel offload dev enp8s0f0 dir in Error: mlx5_core: Device failed to offload this state. The dmesg error is: mlx5_core 0000:03:00.0: ipsec_miss_create:578:(pid 311797): fail to create= IPsec miss_rule err=3D-22 Fix it by adding a new miss level to avoid the error. Fixes: 7d9e292ecd67 ("net/mlx5e: Move IPSec policy check after decryption") Signed-off-by: Jianbo Liu Signed-off-by: Chris Mi Signed-off-by: Lama Kayal Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/fs.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c | 3 ++- drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 4 ++-- 4 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/fs.h b/drivers/net/= ethernet/mellanox/mlx5/core/en/fs.h index 9560fcba643f..ac65e3191480 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/fs.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/fs.h @@ -92,6 +92,7 @@ enum { MLX5E_ACCEL_FS_ESP_FT_LEVEL =3D MLX5E_INNER_TTC_FT_LEVEL + 1, MLX5E_ACCEL_FS_ESP_FT_ERR_LEVEL, MLX5E_ACCEL_FS_POL_FT_LEVEL, + MLX5E_ACCEL_FS_POL_MISS_FT_LEVEL, MLX5E_ACCEL_FS_ESP_FT_ROCE_LEVEL, #endif }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h b/dri= vers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h index ffcd0cdeb775..23703f28386a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h @@ -185,6 +185,7 @@ struct mlx5e_ipsec_rx_create_attr { u32 family; int prio; int pol_level; + int pol_miss_level; int sa_level; int status_level; enum mlx5_flow_namespace_type chains_ns; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c index 98b6a3a623f9..65dc3529283b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c @@ -747,6 +747,7 @@ static void ipsec_rx_create_attr_set(struct mlx5e_ipsec= *ipsec, attr->family =3D family; attr->prio =3D MLX5E_NIC_PRIO; attr->pol_level =3D MLX5E_ACCEL_FS_POL_FT_LEVEL; + attr->pol_miss_level =3D MLX5E_ACCEL_FS_POL_MISS_FT_LEVEL; attr->sa_level =3D MLX5E_ACCEL_FS_ESP_FT_LEVEL; attr->status_level =3D MLX5E_ACCEL_FS_ESP_FT_ERR_LEVEL; attr->chains_ns =3D MLX5_FLOW_NAMESPACE_KERNEL; @@ -833,7 +834,7 @@ static int ipsec_rx_chains_create_miss(struct mlx5e_ips= ec *ipsec, =20 ft_attr.max_fte =3D 1; ft_attr.autogroup.max_num_groups =3D 1; - ft_attr.level =3D attr->pol_level; + ft_attr.level =3D attr->pol_miss_level; ft_attr.prio =3D attr->prio; =20 ft =3D mlx5_create_auto_grouped_flow_table(attr->ns, &ft_attr); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.c index cb165085a4c1..db552c012b4f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -114,9 +114,9 @@ #define ETHTOOL_NUM_PRIOS 11 #define ETHTOOL_MIN_LEVEL (KERNEL_MIN_LEVEL + ETHTOOL_NUM_PRIOS) /* Vlan, mac, ttc, inner ttc, {UDP/ANY/aRFS/accel/{esp, esp_err}}, IPsec p= olicy, - * {IPsec RoCE MPV,Alias table},IPsec RoCE policy + * IPsec policy miss, {IPsec RoCE MPV,Alias table},IPsec RoCE policy */ -#define KERNEL_NIC_PRIO_NUM_LEVELS 10 +#define KERNEL_NIC_PRIO_NUM_LEVELS 11 #define KERNEL_NIC_NUM_PRIOS 1 /* One more level for tc, and one more for promisc */ #define KERNEL_MIN_LEVEL (KERNEL_NIC_PRIO_NUM_LEVELS + 2) --=20 2.31.1