From nobody Thu Oct 2 18:17:14 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77CFF1E8322; Sun, 14 Sep 2025 14:10:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757859026; cv=none; b=ZkA8MUODaoV22xGHGK1D9lrq086PYGhP87WP2Wv4Hm4zaMe6Z8ZVmTuNXo3dDB5AbnHzGJ5t4Qu+S7sOu/n/jlNoG3B0+4DFzzWG7SC1/Ln4jr+jl83VfZ1cB1dTjRV2pOCb4Bvc7dwSP+Ht5baD0tDfWhy+AwnX8t181ghmnp4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757859026; c=relaxed/simple; bh=gpI38ZxVfLy7m/MvVBoM/0OoLn3CKGWk0bp/xqaT5HI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RG4fkoZ8dT2ATf4KCCw7JweIGSmwIeWroyBtdVWys+65CuD/ujVlOKTcuc3r0Zx72tmWIh6xpEOi6lBsdVoPVSeOJXcPdSI935VYRbUW8gfi0A7157QbP9Egp+ytt45KUmtn9jFNesn4kUnA373nu3G59zzmeOoMyhqR7N9hXR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OqpcHhYN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OqpcHhYN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 86B87C4CEF0; Sun, 14 Sep 2025 14:10:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757859025; bh=gpI38ZxVfLy7m/MvVBoM/0OoLn3CKGWk0bp/xqaT5HI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OqpcHhYNZxntomWz3oB7r+pS2dQcYhtebr4WSQ/5568sgGdKqSsjp1wjo3pSKaPRD vWUn7ZMbaVcCEwUoKRQp45UIuU2tILrOEIJfBoX4qhGPpHbdwnRwh7esS5N66LY2Mc UVYAcTbMR+EElgOULsi/jTSLuScVkkWTmAA5CvTbJJiszsRIw6jj8BbnEw5uZaqA4k B5SGGPwIwNWL4eoaWzXDpoe8O1UpdM8G5bHBHRxFU9emt1jC3TqcCOgpHnltxC1nEc ciQ8ZQ9PsilVC1izSfFxvWWKJKeukiY6qDh34jsmLIQhRd2dgL+FlvU2rx7TPtk5Qt gBMK/53IE7XPA== From: "Masami Hiramatsu (Google)" To: Steven Rostedt , Peter Zijlstra , Ingo Molnar , x86@kernel.org Cc: Jinchao Wang , Mathieu Desnoyers , Masami Hiramatsu , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , Alexander Shishkin , Ian Rogers , linux-kernel@vger.kernel.org, linux-trace-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: [PATCH v4 4/8] HWBP: Add modify_wide_hw_breakpoint_local() API Date: Sun, 14 Sep 2025 23:10:19 +0900 Message-ID: <175785901987.234168.7878600292216531453.stgit@devnote2> X-Mailer: git-send-email 2.43.0 In-Reply-To: <175785897434.234168.6798590787777427098.stgit@devnote2> References: <175785897434.234168.6798590787777427098.stgit@devnote2> User-Agent: StGit/0.19 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Masami Hiramatsu (Google) Add modify_wide_hw_breakpoint_local() arch-wide interface which allows hwbp users to update watch address on-line. This is available if the arch supports CONFIG_HAVE_REINSTALL_HW_BREAKPOINT. Note that this allows to change the type only for compatible types, because it does not release and reserve the hwbp slot based on type. For instance, you can not change HW_BREAKPOINT_W to HW_BREAKPOINT_X. Signed-off-by: Masami Hiramatsu (Google) --- Changes in v4: - Update kerneldoc comment about modify_wide_hw_breakpoint_local according to Randy's comment. Changes in v2: - Check type compatibility by checking slot. (Thanks Jinchao!) --- arch/Kconfig | 10 ++++++++++ arch/x86/Kconfig | 1 + include/linux/hw_breakpoint.h | 6 ++++++ kernel/events/hw_breakpoint.c | 37 +++++++++++++++++++++++++++++++++++++ 4 files changed, 54 insertions(+) diff --git a/arch/Kconfig b/arch/Kconfig index d1b4ffd6e085..e4787fc814df 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -418,6 +418,16 @@ config HAVE_MIXED_BREAKPOINTS_REGS Select this option if your arch implements breakpoints under the latter fashion. =20 +config HAVE_REINSTALL_HW_BREAKPOINT + bool + depends on HAVE_HW_BREAKPOINT + help + Depending on the arch implementation of hardware breakpoints, + some of them are able to update the breakpoint configuration + without release and reserve the hardware breakpoint register. + What configuration is able to update depends on hardware and + software implementation. + config HAVE_USER_RETURN_NOTIFIER bool =20 diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 58d890fe2100..49d4ce2af94c 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -247,6 +247,7 @@ config X86 select HAVE_FUNCTION_TRACER select HAVE_GCC_PLUGINS select HAVE_HW_BREAKPOINT + select HAVE_REINSTALL_HW_BREAKPOINT select HAVE_IOREMAP_PROT select HAVE_IRQ_EXIT_ON_IRQ_STACK if X86_64 select HAVE_IRQ_TIME_ACCOUNTING diff --git a/include/linux/hw_breakpoint.h b/include/linux/hw_breakpoint.h index db199d653dd1..ea373f2587f8 100644 --- a/include/linux/hw_breakpoint.h +++ b/include/linux/hw_breakpoint.h @@ -81,6 +81,9 @@ register_wide_hw_breakpoint(struct perf_event_attr *attr, perf_overflow_handler_t triggered, void *context); =20 +extern int modify_wide_hw_breakpoint_local(struct perf_event *bp, + struct perf_event_attr *attr); + extern int register_perf_hw_breakpoint(struct perf_event *bp); extern void unregister_hw_breakpoint(struct perf_event *bp); extern void unregister_wide_hw_breakpoint(struct perf_event * __percpu *cp= u_events); @@ -124,6 +127,9 @@ register_wide_hw_breakpoint(struct perf_event_attr *att= r, perf_overflow_handler_t triggered, void *context) { return NULL; } static inline int +modify_wide_hw_breakpoint_local(struct perf_event *bp, + struct perf_event_attr *attr) { return -ENOSYS; } +static inline int register_perf_hw_breakpoint(struct perf_event *bp) { return -ENOSYS; } static inline void unregister_hw_breakpoint(struct perf_event *bp) { } static inline void diff --git a/kernel/events/hw_breakpoint.c b/kernel/events/hw_breakpoint.c index 8ec2cb688903..5ee1522a99c9 100644 --- a/kernel/events/hw_breakpoint.c +++ b/kernel/events/hw_breakpoint.c @@ -887,6 +887,43 @@ void unregister_wide_hw_breakpoint(struct perf_event *= __percpu *cpu_events) } EXPORT_SYMBOL_GPL(unregister_wide_hw_breakpoint); =20 +/** + * modify_wide_hw_breakpoint_local - update breakpoint config for local CPU + * @bp: the hwbp perf event for this CPU + * @attr: the new attribute for @bp + * + * This does not release and reserve the slot of a HWBP; it just reuses the + * current slot on local CPU. So the users must update the other CPUs by + * themselves. + * Also, since this does not release/reserve the slot, this can not change= the + * type to incompatible type of the HWBP. + * Return err if attr is invalid or the CPU fails to update debug register + * for new @attr. + */ +#ifdef CONFIG_HAVE_REINSTALL_HW_BREAKPOINT +int modify_wide_hw_breakpoint_local(struct perf_event *bp, + struct perf_event_attr *attr) +{ + int ret; + + if (find_slot_idx(bp->attr.bp_type) !=3D find_slot_idx(attr->bp_type)) + return -EINVAL; + + ret =3D hw_breakpoint_arch_parse(bp, attr, counter_arch_bp(bp)); + if (ret) + return ret; + + return arch_reinstall_hw_breakpoint(bp); +} +#else +int modify_wide_hw_breakpoint_local(struct perf_event *bp, + struct perf_event_attr *attr) +{ + return -EOPNOTSUPP; +} +#endif +EXPORT_SYMBOL_GPL(modify_wide_hw_breakpoint_local); + /** * hw_breakpoint_is_used - check if breakpoints are currently used *