From nobody Thu Oct 2 20:44:48 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29532315789; Thu, 11 Sep 2025 10:29:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757586548; cv=none; b=m5TeP9NbABTGPhQtiROw50oCl4vIlJK39pSDAweXAnfe/lCf6+4Zq/6y8Ro6Dnm9rhNZK2k5AtQtS6fDG7LW7QHW/P1OhUy+KmvM5WE/6FqEYCKIjZyhYB0Bs5aiL8tFz/wekxlO/ZL2UL58VchVdYHylBVAS5G9+HbN0OREnzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757586548; c=relaxed/simple; bh=CvTwIwObffw2f/flWXoMkBXXTqr5z2Qx7zAdMWCSfYw=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=Y8dg8mDqOM8bSM4kvCJDVSndDBKDNoCHjd315W8LpMnQXNTtNQWREHIiAB8+iebJ15R8dgRI1jPJdB81HBcBaOkwQ6P7GDrZDMHJZ71zcsj2KWLjhefgzC5vjoy/76VU5YVvYDxvDz6JFQSi0kmd3gMr3tPMFIiziIY0yH5hucE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2gxM4Vtz; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Yhp4Vr/y; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2gxM4Vtz"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Yhp4Vr/y" Date: Thu, 11 Sep 2025 10:29:04 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1757586545; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=J3S5S9vSIUYpWkseec4Pgq0mxxpUs4WEJRoqEUyKSDQ=; b=2gxM4VtzQVKv+jMYKiLe0clsHc9Mq66O8kp+nnFxZtXo34ut15G8c4VFC+tHB6gdkFzAcK H0eVO2vNJDUD8+A17TeztDE6Juw4N5i25WNn3RNnl//6+SQ5sZJGuxYroQcqJ8Mw0MdpJt UAV/O2qlPEvfWb2+zdudSrXiYPhF+Le3GRGNei/C3Qpi6K00Rzj7/Uwq9GdJEEEE9WGWQE tShvMs/umcoAYLBsUkuN7sHuSHrmkj39FClM0eBnXua3g3pfIqV6T7yXS9vmkGnkcv7Pn7 qdH5yiopUILkTTtJvnzEnihxOWcJ9RyLgho1ehVdxOKZMTH9eAdQTEdAXpsYhw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1757586545; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=J3S5S9vSIUYpWkseec4Pgq0mxxpUs4WEJRoqEUyKSDQ=; b=Yhp4Vr/yy5dX00xyD+U7eqDEpLRutKbIolk7klIVZDF50Tuy9WY8fh1Mff1bjds78q3e50 FSdvRcTt8e1vmNDw== From: "tip-bot2 for Yazen Ghannam" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: ras/core] x86/mce: Set CR4.MCE last during init Cc: Yazen Ghannam , "Borislav Petkov (AMD)" , Nikolay Borisov , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <175758654433.709179.12735346460717574219.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the ras/core branch of tip: Commit-ID: cfffcf97997bd35f4a59e035523d1762568bdbad Gitweb: https://git.kernel.org/tip/cfffcf97997bd35f4a59e035523d17625= 68bdbad Author: Yazen Ghannam AuthorDate: Mon, 08 Sep 2025 15:40:30=20 Committer: Borislav Petkov (AMD) CommitterDate: Thu, 11 Sep 2025 12:22:20 +02:00 x86/mce: Set CR4.MCE last during init Set the CR4.MCE bit as the last step during init. This brings the MCA init order closer to what is described in the x86 docs. x86 docs: AMD Intel MCG_CTL MCA_CONFIG MCG_EXT_CTL MCi_CTL MCi_CTL MCG_CTL CR4.MCE CR4.MCE Current Linux: AMD Intel CR4.MCE CR4.MCE MCG_CTL MCG_CTL MCA_CONFIG MCG_EXT_CTL MCi_CTL MCi_CTL Updated Linux: AMD Intel MCG_CTL MCG_CTL MCA_CONFIG MCG_EXT_CTL MCi_CTL MCi_CTL CR4.MCE CR4.MCE The new init flow will match Intel's docs, but there will still be a mismatch for AMD regarding MCG_CTL. However, there is no known issue with t= his ordering, so leave it for now. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Nikolay Borisov Link: https://lore.kernel.org/20250908-wip-mca-updates-v6-0-eef5d6c74b9c@am= d.com --- arch/x86/kernel/cpu/mce/core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 0326fbb..9e31834 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1850,8 +1850,6 @@ static void __mcheck_cpu_init_generic(void) { u64 cap; =20 - cr4_set_bits(X86_CR4_MCE); - rdmsrq(MSR_IA32_MCG_CAP, cap); if (cap & MCG_CTL_P) wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); @@ -2276,6 +2274,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) __mcheck_cpu_init_vendor(c); __mcheck_cpu_init_prepare_banks(); __mcheck_cpu_setup_timer(); + cr4_set_bits(X86_CR4_MCE); } =20 /* @@ -2443,6 +2442,7 @@ static void mce_syscore_resume(void) __mcheck_cpu_init_generic(); __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); __mcheck_cpu_init_prepare_banks(); + cr4_set_bits(X86_CR4_MCE); } =20 static struct syscore_ops mce_syscore_ops =3D { @@ -2462,6 +2462,7 @@ static void mce_cpu_restart(void *data) __mcheck_cpu_init_generic(); __mcheck_cpu_init_prepare_banks(); __mcheck_cpu_init_timer(); + cr4_set_bits(X86_CR4_MCE); } =20 /* Reinit MCEs after user configuration changes */