From nobody Thu Oct 2 20:44:10 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D62A4313E2C; Thu, 11 Sep 2025 10:29:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757586545; cv=none; b=Pz4SbKsO5oAgWEUCkCLjlfipbq8UOSBG+lGUkabQrrSI/0B1l1HCvi2iJ/Lcj9BGzbkM461HE2cjZyyS5O7QuTNZD2NMzsE6ozK+/1nVrAipRi3BVgzc3F4l8h7Prc9cYUK5o1eqE7S9tfW9PC33294c4Su43pDuku7VQWWqJa4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757586545; c=relaxed/simple; bh=rPhj1AM5Q5TVakSIW3Jo0lrmR8NFKWKn3qdbnOoVQ/o=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=o+NH7g5jLYboLRf46LF+lctjVfL405yRlTXQKBJHt69XaV+Lx0PvQdYi/oB8ylP7Pk1G4jtg6oFEMOXvkefpGugrYSPn8YOZun8+U+Hu/H9B3sJnFEOqIQAr++eEp3t+j7AVxpFuGfCWXsGJYwkFYn7TXUj8cI1aaU2bv4qQG2g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=jEZ8otLm; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=tKsWdMyj; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jEZ8otLm"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="tKsWdMyj" Date: Thu, 11 Sep 2025 10:29:01 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1757586542; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=YwTzikQUVCXD+LlKDopQyFxlQ8ZQtNErBjjZRwBjaxQ=; b=jEZ8otLm46Fzq3Nsp8F79fZlnF7uLmzdNdtUUIUqTVbsaIGlJHQCFWQ2HOhpvyQLXpQrV1 9inRmz31YTrVCbizgn6M3+1Ty10sD2a/IEGNY2k7uFq5QcSu0dkg1Plpx9BSI9TN7AWVl8 1X9Cf1L2jUuQnmje9y0in6tf2tByd+tczd8VRzoEwqUuK6XNdEpPkjvbUf3LxdbRUziuPq dsueLgiSlJKyhmCSBzGQk4oPQWElg1iYlsIU15INY3D9Icn1U7sPeUFI0dYzwgxQ0EhNYC kSZfbrdUZBTPpN4FDWZAZfebGUYiqr0UFIlFfQlpqqo8PAhy8WhEfPfQangJiw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1757586542; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=YwTzikQUVCXD+LlKDopQyFxlQ8ZQtNErBjjZRwBjaxQ=; b=tKsWdMyjGGrlZN3UXOOJBBGNp3vYaiNf3xgSFKbnjSZOumGzkkrtxKS+o9jNmw7EpNbsup o9hvdiC+3UfKePAg== From: "tip-bot2 for Yazen Ghannam" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: ras/core] x86/mce: Do 'UNKNOWN' vendor check early Cc: Yazen Ghannam , "Borislav Petkov (AMD)" , Qiuxu Zhuo , Tony Luck , Nikolay Borisov , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <175758654121.709179.17450649308580079896.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the ras/core branch of tip: Commit-ID: a46b2bbe1e36e7faab5010f68324b7d191c5c09f Gitweb: https://git.kernel.org/tip/a46b2bbe1e36e7faab5010f68324b7d19= 1c5c09f Author: Yazen Ghannam AuthorDate: Mon, 08 Sep 2025 15:40:33=20 Committer: Borislav Petkov (AMD) CommitterDate: Thu, 11 Sep 2025 12:23:03 +02:00 x86/mce: Do 'UNKNOWN' vendor check early The 'UNKNOWN' vendor check is handled as a quirk that is run on each online CPU. However, all CPUs are expected to have the same vendor. Move the 'UNKNOWN' vendor check to the BSP-only init so it is done early and once. Remove the unnecessary return value from the quirks check. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Qiuxu Zhuo Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Tested-by: Tony Luck Link: https://lore.kernel.org/20250908-wip-mca-updates-v6-0-eef5d6c74b9c@am= d.com --- arch/x86/kernel/cpu/mce/core.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index a8cb7ff..515942c 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1977,14 +1977,11 @@ static void apply_quirks_zhaoxin(struct cpuinfo_x86= *c) } =20 /* Add per CPU specific workarounds here */ -static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) +static void __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) { struct mca_config *cfg =3D &mca_cfg; =20 switch (c->x86_vendor) { - case X86_VENDOR_UNKNOWN: - pr_info("unknown CPU type - not enabling MCE support\n"); - return false; case X86_VENDOR_AMD: apply_quirks_amd(c); break; @@ -2000,8 +1997,6 @@ static bool __mcheck_cpu_apply_quirks(struct cpuinfo_= x86 *c) cfg->monarch_timeout =3D 0; if (cfg->bootlog !=3D 0) cfg->panic_timeout =3D 30; - - return true; } =20 static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) @@ -2240,6 +2235,12 @@ void mca_bsp_init(struct cpuinfo_x86 *c) if (!mce_available(c)) return; =20 + if (c->x86_vendor =3D=3D X86_VENDOR_UNKNOWN) { + mca_cfg.disabled =3D 1; + pr_info("unknown CPU type - not enabling MCE support\n"); + return; + } + mce_flags.overflow_recov =3D cpu_feature_enabled(X86_FEATURE_OVERFLOW_REC= OV); mce_flags.succor =3D cpu_feature_enabled(X86_FEATURE_SUCCOR); mce_flags.smca =3D cpu_feature_enabled(X86_FEATURE_SMCA); @@ -2274,10 +2275,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) =20 __mcheck_cpu_cap_init(); =20 - if (!__mcheck_cpu_apply_quirks(c)) { - mca_cfg.disabled =3D 1; - return; - } + __mcheck_cpu_apply_quirks(c); =20 if (!mce_gen_pool_init()) { mca_cfg.disabled =3D 1;