From nobody Thu Oct 2 20:44:52 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10567313532; Thu, 11 Sep 2025 10:29:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757586543; cv=none; b=YjSBY4PEPQ25xhXd2SVPzMXd2CVeot+y7mnSvVZBXIEk3XVBrMjS1wX/weHWYlGJE3mV77iLuuWo5xXNbVb2YmBRzqICdTNO3q4hlULJ8xlX+tmsukXU7q62I2/mDDhtR/YFiSPxW1kd8cmISvk3TzSQuiDDYIdivdLJ3RDXVrs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757586543; c=relaxed/simple; bh=JoQE42PndkYh2ZpH5Z/I4EBYdqTQ/rC/Pi07KeUpUAw=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=DY1M+Yy3jNyKR5NfNAPocTbjZQBp1gE1PeiDYj30yLAV+5QQux/bw8qyks68ZCXW7tDbDeqrdUUIvuObKUdGBsrv3n+BNhnSwtB6Coq/MXeIQHOU025io4R+ehX+c0vI2yX2zIVvN2IU06CmQPdK9d9AvqeGnYlI8I2v/5s4SWg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=XLdcD+sp; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=bKPKvChg; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="XLdcD+sp"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="bKPKvChg" Date: Thu, 11 Sep 2025 10:28:59 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1757586540; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=g5WhIfJRvCyVG8NUvrewQT8NwvgG7N7trn54du6Ooxg=; b=XLdcD+sp8ARyZpxB1NTjKTjtKY6kXovhwIvZ1Ssrta7qSpvOdYFcrVJA7GkLRSvmPwm1Ja hEjqnace3Y9kOa7zTuwfqYNgwnXW2nkvAPnK6e0bY6Z2iq33qk3wBLHWBgg1aSiZ9Q0BPo 2ur/kPX1Nu11zwracGrAt4hz7zP6fkXtgwPQ49lYF2fQcjRr8qwK1RJddTe1AQ1NuLNitd xa9YYef//efQYXn32Jtij7dAke0978ut8bNsAGcwAqo6odBOU77afSXtHh5H8yHno5A3Xr CP0HW75z4o9cvBRN7gplnZ8hztacXw5/l+6OvCKccfqCYJu8BoB33PxhlwgE9A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1757586540; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=g5WhIfJRvCyVG8NUvrewQT8NwvgG7N7trn54du6Ooxg=; b=bKPKvChgtZeJJCl2+i0hZPPibiVaJKQRIGbHcMd50bXu6+FKNutll1lRM/1LT8o7gVn+bS WFmaTlsp3fws5fCA== From: "tip-bot2 for Yazen Ghannam" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: ras/core] x86/mce: Move machine_check_poll() status checks to helper functions Cc: Yazen Ghannam , "Borislav Petkov (AMD)" , Qiuxu Zhuo , Tony Luck , Nikolay Borisov , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <175758653917.709179.7141514378637292570.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the ras/core branch of tip: Commit-ID: 91af6842e9945d064401ed2d6e91539a619760d1 Gitweb: https://git.kernel.org/tip/91af6842e9945d064401ed2d6e91539a6= 19760d1 Author: Yazen Ghannam AuthorDate: Mon, 08 Sep 2025 15:40:35=20 Committer: Borislav Petkov (AMD) CommitterDate: Thu, 11 Sep 2025 12:23:22 +02:00 x86/mce: Move machine_check_poll() status checks to helper functions There are a number of generic and vendor-specific status checks in machine_check_poll(). These are used to determine if an error should be skipped. Move these into helper functions. Future vendor-specific checks will be added to the helpers. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Qiuxu Zhuo Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Tested-by: Tony Luck Link: https://lore.kernel.org/20250908-wip-mca-updates-v6-0-eef5d6c74b9c@am= d.com --- arch/x86/kernel/cpu/mce/core.c | 88 ++++++++++++++++++--------------- 1 file changed, 48 insertions(+), 40 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 7fd86c8..5dec0da 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -715,6 +715,52 @@ static noinstr void mce_read_aux(struct mce_hw_err *er= r, int i) DEFINE_PER_CPU(unsigned, mce_poll_count); =20 /* + * Newer Intel systems that support software error + * recovery need to make additional checks. Other + * CPUs should skip over uncorrected errors, but log + * everything else. + */ +static bool ser_should_log_poll_error(struct mce *m) +{ + /* Log "not enabled" (speculative) errors */ + if (!(m->status & MCI_STATUS_EN)) + return true; + + /* + * Log UCNA (SDM: 15.6.3 "UCR Error Classification") + * UC =3D=3D 1 && PCC =3D=3D 0 && S =3D=3D 0 + */ + if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S)) + return true; + + return false; +} + +static bool should_log_poll_error(enum mcp_flags flags, struct mce_hw_err = *err) +{ + struct mce *m =3D &err->m; + + /* If this entry is not valid, ignore it. */ + if (!(m->status & MCI_STATUS_VAL)) + return false; + + /* + * If we are logging everything (at CPU online) or this + * is a corrected error, then we must log it. + */ + if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC)) + return true; + + if (mca_cfg.ser) + return ser_should_log_poll_error(m); + + if (m->status & MCI_STATUS_UC) + return false; + + return true; +} + +/* * Poll for corrected events or events that happened before reset. * Those are just logged through /dev/mcelog. * @@ -765,48 +811,10 @@ void machine_check_poll(enum mcp_flags flags, mce_ban= ks_t *b) if (!mca_cfg.cmci_disabled) mce_track_storm(m); =20 - /* If this entry is not valid, ignore it */ - if (!(m->status & MCI_STATUS_VAL)) + /* Verify that the error should be logged based on hardware conditions. = */ + if (!should_log_poll_error(flags, &err)) continue; =20 - /* - * If we are logging everything (at CPU online) or this - * is a corrected error, then we must log it. - */ - if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC)) - goto log_it; - - /* - * Newer Intel systems that support software error - * recovery need to make additional checks. Other - * CPUs should skip over uncorrected errors, but log - * everything else. - */ - if (!mca_cfg.ser) { - if (m->status & MCI_STATUS_UC) - continue; - goto log_it; - } - - /* Log "not enabled" (speculative) errors */ - if (!(m->status & MCI_STATUS_EN)) - goto log_it; - - /* - * Log UCNA (SDM: 15.6.3 "UCR Error Classification") - * UC =3D=3D 1 && PCC =3D=3D 0 && S =3D=3D 0 - */ - if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S)) - goto log_it; - - /* - * Skip anything else. Presumption is that our read of this - * bank is racing with a machine check. Leave the log alone - * for do_machine_check() to deal with it. - */ - continue; - -log_it: mce_read_aux(&err, i); m->severity =3D mce_severity(m, NULL, NULL, false); /*