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Thu, 11 Sep 2025 00:10:41 -0700 From: Tariq Toukan To: Saeed Mahameed , Leon Romanovsky CC: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , Tariq Toukan , "Mark Bloch" , Sabrina Dubroca , , , , Gal Pressman , Dragos Tatulea , Carolina Jubran , Jianbo Liu Subject: [PATCH mlx5-next 3/3] net/mlx5e: Prevent WQE metadata conflicts between timestamping and offloads Date: Thu, 11 Sep 2025 10:10:19 +0300 Message-ID: <1757574619-604874-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1757574619-604874-1-git-send-email-tariqt@nvidia.com> References: <1757574619-604874-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD4:EE_|SJ5PPFD5E8DE351:EE_ X-MS-Office365-Filtering-Correlation-Id: 3bdc9808-483b-47dd-150f-08ddf1025c41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?rL4z/5p59VZ3/1oL3hLa1inSBWLgLgRh82FXu5Ij8xJlVU4qls5t1HzHuuLn?= =?us-ascii?Q?iR8lspM8tdRUnjc9QQgkqLEmHo+G2a78PmmvRkAG3brZsQLI/DEIPsA1DcpP?= =?us-ascii?Q?XmoWVw3y3rpLtx+5HxxXNivgcLOAA/yVMHvwKL6a5dza7zrfvZxXZwe9048i?= =?us-ascii?Q?5z6E7cxjylYCK6zu5TDfEDaj844qOOpEKiQsZb2AuBbi+kbrXMenJhl7vLt4?= =?us-ascii?Q?xgo+mxQuRylFmXF4ZIt2KRBDCSsl/mtH68NpvB0M3y6cqdmQ1nP/KSa2HpFH?= =?us-ascii?Q?FbYJQJSx7bewl2IFkFTHIdUhKoSqk6S4E5hYhehs95W7IptGdzGwfS1T0xVr?= =?us-ascii?Q?rKP46FjTh3Z0t2D6Kw4RzZ0pS6kkkgjZFowgZgjP9RkvKg+YS5NLuG/fgO8t?= =?us-ascii?Q?vRD0mwOY/GgzfqtAFyGgBN/bKdZ9zQPu4XIhXEjz/JN42XxahlGzXiIZ9XF6?= =?us-ascii?Q?xQ2Xnml/KelF2lV5xRMwgHIp//eVcKa3iE73YG3thVfImnvZtBFq41L3vttI?= =?us-ascii?Q?8zDbtoU81KDzjAzgxpUmJGzuj2PyHNrZntZ/3mMeo3KDmezmW7EnhQTHTetZ?= =?us-ascii?Q?t+i99yguqWBXgHnzV8NjeIEa/GgVskQp9KH3cIo32sKuXwrBmm9J/h5lA1lf?= =?us-ascii?Q?1XIImFsZeqI4kLQ6ca6mHG5FtaDZBiqVxquEoKyln6LkbGeKG31ZqhpS7+Lq?= =?us-ascii?Q?ATTvaaNPj8nSChf8M43DBIYLUGLjyBtkUZJeGwAwfM/Z2n3+yI+VSxlRGXQl?= =?us-ascii?Q?0qXezjc+ZbacVAykXvtoDv4t1+v4sJ4zaOhBObptuXFIvTA4MUQ97PJd9n1y?= =?us-ascii?Q?IZGaNbqGk8GL+sNGFkBFmr1j0F5sN6rC6C/2Lsa2aHAB8Tj4FZHIUNQCzzc2?= =?us-ascii?Q?yVtaWeNMfN2o2eK02d1hW6oYyh70Dfv8k2grpt5zXEbUyAS4VNK06pxmNF7a?= =?us-ascii?Q?99M2UuojbwANnHUR1H5LURBYjp9L2rI7j7nPGUANhxhB9tYS46j2OEIuxHZK?= =?us-ascii?Q?I5X27hwUgDGhjdCAmxUJhTYQikKlFcG85l7vCqNFiS5koZGjSGUmtvsAQ6uq?= =?us-ascii?Q?HjNJYf/YuP7AthkSrOCKcRXVr7+8aWoExpMyWyMz664TM1ORfpMeFg9b7alF?= =?us-ascii?Q?1BpuFhPuay6mysBGjThlBtRD7iOCoGHkRg95jKNcCgrxt0h4E1T9sn4IcO8o?= =?us-ascii?Q?K3Bf5afA1V3IjyykXnZVzoXAhA+RRA4CARzTsOcnJ1LnewtNeN5dCvryzjDO?= =?us-ascii?Q?Hi/aHrBSuOpVwBljH0jiyp+C05S7jNAdPa7T+K/j9DI/rQ62UX6gIfGsiTrN?= =?us-ascii?Q?7fQTgWqCooX6aYPbv7gFu39r7JVr84M/ZeHQkMvyEJVu9e79Zr4mdxMNtolg?= =?us-ascii?Q?JHEsBvAT5dUPpRfQIJTObHGfXP8ete7jclWGZSWyHoweS5oKrxky2/fb9K4d?= =?us-ascii?Q?StqXRr+B37Ork9qBT9svmyzq+j5tmMNOAg8ML/LLrFt08e/cUsHHzvoGklyB?= =?us-ascii?Q?Ty6SDUXc//HJx6NBUZSuCKqcKRHCqny4Cs9f?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2025 07:10:59.4613 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bdc9808-483b-47dd-150f-08ddf1025c41 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPFD5E8DE351 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Update the WQE metadata assignment to avoid overriding existing metadata when setting the sysport timestamp ID. Since timestamp IDs are limited to 256 values, they use only the lower 8 bits of the metadata field. To avoid conflicts, move IPsec and MACsec metadata ID to bits 8 and 9, and shift the MACsec fs_id accordingly. This ensures safe coexistence of timestamping and offload features that use the same metadata field. Signed-off-by: Carolina Jubran Reviewed-by: Jianbo Liu Reviewed-by: Patrisious Haddad Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/en_tx.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c | 2 +- include/linux/mlx5/qp.h | 5 +++-- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_tx.c index 319061d31602..6c55b67b7335 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c @@ -653,7 +653,7 @@ static void mlx5e_cqe_ts_id_eseg(struct mlx5e_ptpsq *pt= psq, struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg) { if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) - eseg->flow_table_metadata =3D + eseg->flow_table_metadata |=3D cpu_to_be32(mlx5e_ptp_metadata_fifo_peek(&ptpsq->metadata_freelist)); } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c b/driv= ers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c index 9ec450603176..e6be2f01daf4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c @@ -2219,7 +2219,7 @@ static int mlx5_macsec_fs_add_roce_rule_tx(struct mlx= 5_macsec_fs *macsec_fs, u32 mlx5_macsec_fs_set_tx_fs_id(fs_id)); MLX5_SET(set_action_in, action, offset, MLX5_ETH_WQE_FT_META_MACSEC_SHIFT); - MLX5_SET(set_action_in, action, length, 32); + MLX5_SET(set_action_in, action, length, 8); =20 modify_hdr =3D mlx5_modify_header_alloc(mdev, MLX5_FLOW_NAMESPACE_RDMA_TX= _MACSEC, 1, action); diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h index b21be7630575..d67aedc6ea68 100644 --- a/include/linux/mlx5/qp.h +++ b/include/linux/mlx5/qp.h @@ -251,8 +251,9 @@ enum { MLX5_ETH_WQE_SWP_OUTER_L4_UDP =3D 1 << 5, }; =20 -/* Base shift for metadata bits used by timestamping, IPsec, and MACsec */ -#define MLX5_ETH_WQE_FT_META_SHIFT 0 +/* Metadata bits 0-7 are used by timestamping */ +/* Base shift for metadata bits used by IPsec and MACsec */ +#define MLX5_ETH_WQE_FT_META_SHIFT 8 =20 enum { MLX5_ETH_WQE_FT_META_IPSEC =3D BIT(0) << MLX5_ETH_WQE_FT_META_SHIFT, --=20 2.31.1