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Thu, 11 Sep 2025 00:10:32 -0700 From: Tariq Toukan To: Saeed Mahameed , Leon Romanovsky CC: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , Tariq Toukan , "Mark Bloch" , Sabrina Dubroca , , , , Gal Pressman , Dragos Tatulea , Carolina Jubran , Jianbo Liu Subject: [PATCH mlx5-next 1/3] net/mlx5: Remove VLAN insertion fields from WQE Ether segment Date: Thu, 11 Sep 2025 10:10:17 +0300 Message-ID: <1757574619-604874-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1757574619-604874-1-git-send-email-tariqt@nvidia.com> References: <1757574619-604874-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD79:EE_|MN2PR12MB4078:EE_ X-MS-Office365-Filtering-Correlation-Id: cd390eda-a96f-46e2-494d-08ddf1025763 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?a30IjHTMer9KTu5SDGhuPg6D6+LlpjvYKL5RqGUSk3PTC019kxyB2I9ZXJs6?= =?us-ascii?Q?L6pxtuOOnIcYw6Ycjyo5pVVTkh/gkpjq5MFRQjcwxcVQ/RclIpvL0s/6Qrjj?= =?us-ascii?Q?XiomBG5WFzS9nrq2Avtq9p8pjuOBKKdWjJsnCxpcceQqVmLVA/XvUmmKGxTQ?= =?us-ascii?Q?Txtb5Y2iHg1JHYsWGzYGR9K8iWZbhEJ7PUICFbK+igHhP0/v0MDgFopU+QE0?= =?us-ascii?Q?wQts5v59qsOm/g+2ek8MKITB3jYibsTIXgq4306nX6//cw1kl7XcieBETiIW?= =?us-ascii?Q?kfny47kR1sVlVVr5GPOfnB4tHJul3s/4NWQDd2dLq0L8bosuG8Fh8NuTjM3z?= =?us-ascii?Q?jClxV7pMX2HC7WFwOtXxTTHVesfZwb4cgd3rktinL0g4fTPATSPaSVLo6/Dh?= =?us-ascii?Q?8MbB6LDnZMCihnDG7ZLrcWQj+qsr0osYWjUKKvFstN6aVS1j3pwlLEvO8evr?= =?us-ascii?Q?WWoOZfN1o7jw0L2e3qXFTa7xuBf/hj0+9YzFKVON+4DW6oy95zZ3Xf/iyujQ?= =?us-ascii?Q?7GJqSOcyyXqamBZB/YRgEeua8XBnp8cXbjd1/cqm8VAbavliFvNBajqTK9ni?= =?us-ascii?Q?qHk0LiEksdF+eurhmaoMg6SBeoiFQrRcvnHa96L2NYHWedHLOiKfX3vr/LTj?= =?us-ascii?Q?IsjJvILhO0Le4xwajcYTY6dY4rccwekqEBDCp7vZI1juN5Tkc9NVmjRiiPft?= =?us-ascii?Q?zZxbH0gZM0/Zlut7uNxh80mg/fEBzdZij+a36uAQlghGeIDAxQXp3UlVPLKF?= =?us-ascii?Q?u2FcTXHWWDqYnpJ9Y7Z3pBhwM6W2Nh6I4+WiH4eJ/B8+nNKbeFLLcvByW0Qg?= =?us-ascii?Q?4f7OQsbdfr4pILxSGrzj6JaQl/lBUnmcEsIAVolyE4fnMxk3lzAxmWkiN9US?= =?us-ascii?Q?8WCrKRH0vCTGwl2EZlvQEcwPYtCpeNoFG4kwlhhHmO+PCheUtBv2xUtiV3II?= =?us-ascii?Q?NjCDiLBllhzfNB811jikWCV16X+2ArT0eUZayAnxCp37eHhkh0rZ3xknWB9q?= =?us-ascii?Q?zquODaLMDtW34OLJGbXN/0QbLRZ3EhopOdbwUtHizINttNqLPZTJ5MHVSh6x?= =?us-ascii?Q?BUDj0IdFN1hRIxS98AeBm3egA8ssbR99TX/iOmB1W2Viv9IebSWmEwcmuitd?= =?us-ascii?Q?gAADSDmxILF1WpxH28f7pq7X2L6Bnipg92pV2BaVGTkw6Jp/AoqFkw+XpzNx?= =?us-ascii?Q?LCupS6d+QE1aKA0h8fgRuK63GzhV83O2/AsJI8ohevMaFlZQPZyd/ptRgk4x?= =?us-ascii?Q?ebh9RaP0CScDJAFTqGvhawp/WV1nV47sF1XO8+sGWqGuIlXQrFbGtzxtDpWQ?= =?us-ascii?Q?uSCIM3QEQLEiSfLKLG7Tw8TTglCe4UwFOke1SZ2nr6ikAEQpKIlRykClR8XN?= =?us-ascii?Q?9XdHf5sjEAQC3NsurdO4HCL6/kT3OSq1akeQoQchW5ivNjJf6Gwcrp9t7XDK?= =?us-ascii?Q?FD36d5K/tJHuR6pzWH2taQvf1ZWWJ/ec5QJOyttW8d/5RyAjk7VOM/HAw8lm?= =?us-ascii?Q?wpPX9axYZfBP85IgmSpKT9V2ZHfhU3vbOO5C?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2025 07:10:51.3747 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd390eda-a96f-46e2-494d-08ddf1025763 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD79.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4078 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Now that the driver no longer uses VLAN TX insertion via the WQE Ethernet segment, the related fields and flags can be removed. Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- include/linux/mlx5/qp.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h index fc7eeff99a8a..5546c7bd2c83 100644 --- a/include/linux/mlx5/qp.h +++ b/include/linux/mlx5/qp.h @@ -237,13 +237,11 @@ enum { }; =20 enum { - MLX5_ETH_WQE_SVLAN =3D 1 << 0, MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC =3D 1 << 26, MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC =3D 1 << 27, MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC =3D 3 << 26, MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC =3D 1 << 28, MLX5_ETH_WQE_INSERT_TRAILER =3D 1 << 30, - MLX5_ETH_WQE_INSERT_VLAN =3D 1 << 15, }; =20 enum { @@ -275,10 +273,6 @@ struct mlx5_wqe_eth_seg { DECLARE_FLEX_ARRAY(u8, data); }; } inline_hdr; - struct { - __be16 type; - __be16 vlan_tci; - } insert; __be32 trailer; }; }; --=20 2.31.1 From nobody Thu Oct 2 20:42:51 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2057.outbound.protection.outlook.com [40.107.243.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56CF6266B67; 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Miller" , Tariq Toukan , "Mark Bloch" , Sabrina Dubroca , , , , Gal Pressman , Dragos Tatulea , Carolina Jubran , Jianbo Liu Subject: [PATCH mlx5-next 2/3] net/mlx5: Refactor MACsec WQE metadata shifts Date: Thu, 11 Sep 2025 10:10:18 +0300 Message-ID: <1757574619-604874-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1757574619-604874-1-git-send-email-tariqt@nvidia.com> References: <1757574619-604874-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7B:EE_|DM4PR12MB7765:EE_ X-MS-Office365-Filtering-Correlation-Id: fc7019f1-60ed-495d-8bc7-08ddf1025a6d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?B?RGNwSnpvWXJ6NmNnRml6aEUvTTA3ajhQNzJUbXpJSVlRZVZvRXEzZ0c4MHhC?= =?utf-8?B?Nkc1QTBiM2RmVGFKdklOUlJDbkJNcExSODZPQVljcUtlVEFOOThmK3dnYWtm?= =?utf-8?B?QXVQNEN6d21LbXpyZjZLWHE5SVErWVBlL3RBcE1wVkZuME1RbGN3UG41ZFlr?= =?utf-8?B?c3AxalpWcHNveDFHQi9wMXpOb0trcUdRaXM1YW9NTkZOWEs1bXo0MGxjUmFW?= =?utf-8?B?TTJqcGJEb2s1QWhwYTVEL29pRjJibnltTzVYS1BjSlBCYXJuV1NYaUQzSVBL?= =?utf-8?B?U29yVCs0K3dxdXFIZGNZQU5LQnFtMGlONmtYeE4yVWhOZWx4dHRiNUY2SW5K?= =?utf-8?B?bFZYdXhSMWJBdjI0SHdEVWVuUEFiUVE0anhKblNLV1p5UmR0ejJJYmQrbGFV?= =?utf-8?B?bElSQnVmQjJpYjNRNEJlc1lZQXhjaTJ4VGx6aG5TSlM3eTF3a0hkanNwR2JP?= =?utf-8?B?RndZNkpWMXpKTHZnZlBzeVl2WmRyZFNLVjh6TUxPRFhIcHBEaHFhcEF0ZER3?= =?utf-8?B?WFNsSXBtWURLUWZ4TEY2M2lLSmtmdmJGRzZ5cllOZk14Y1o3RnA3ZDlhK2hv?= =?utf-8?B?aHk4MlF3OTFPSkN6WjBqZy9lZDJPbzhlNzYwTTEwUCtkamlCb1RTVjliYllV?= =?utf-8?B?Z2kzcnYwWTE0QkpWWFJSeW0xU2duNnJhZjdEd3UvR2hWc1htRnlNekdFV1Bh?= =?utf-8?B?SGRUc0syVTV4NXo0NFpzTkp1STRqKy9JTUcvM25Pc0s5SUpJV0U2YVlUQXVJ?= =?utf-8?B?UFVGNkJwSW4zVEt5S2FPUldIQkVIbnFZL0JscG9CeWRaYVVDM2hmbHF2c2Fx?= =?utf-8?B?SlhqY1V6cnhTYXJhc2lORHZYMENHb0drdCthZGIyNzdWME0yTk1IL25YZ3ph?= =?utf-8?B?MDZyeGw0K2h3ZTNTbUFWZmVSdDlwOVpicTNPTXIrN0dFRWpON0Y5YitaV2Ry?= =?utf-8?B?T3Zkd3M3bEo0anpkTHBxUDVWMXFUVzNXa0EvQWxLbDVaOUlXS29adzFZQVNK?= =?utf-8?B?NUtSMHZDVFBOcE5JUWFhTmQ3emtxMXI1eVZyQ25mOWFYTEpPT0htWUlnbkhB?= =?utf-8?B?d2pyOXF1YUdyVW5xSVJtYU1oUklzSTJpM3lLQ3MxV2F1QnV1dzFVWlNLMENv?= =?utf-8?B?Y2xncGt0RWF2U1BjMittVTN3RWFxNFhSMmlYWi9oQVVDV2FjY3dlaFJKYXcv?= =?utf-8?B?SzN2eXdJRXJnSHg2V3dpQWs4dWlYNU1rV1F2OGR3Z29HQTBKWjVNVTZPdFRW?= =?utf-8?B?OTJoTFl5MWNrOEhjWUM3Ymw5cWxhVStpYTRYRjZvRmI2NUdCY2x0ejZjK0xi?= =?utf-8?B?eklpQmNLekhwSG4zSGZPL29EZTZFK1p2NWtJWmlGYkRSS0tyZS9ycFUyZ0NG?= =?utf-8?B?VjUrRDZsVUxWVkRlUFk0NExDRld0b0xsQ1djbkZFakdDTnFmOVRROS95VEFs?= =?utf-8?B?R1huWjRZV29SSlpsTDRKSnQ2UnNqUEFjMDgzRk12YlhNNzJ5U1l0cnFTMzZ4?= =?utf-8?B?eVNUbWtqM05raXRlU09VTnoza0hCMmFwcngzT2ZUQXVFS0hHbkxsa2hQcW9T?= =?utf-8?B?NGE2MWtrQlZTR2d2TjRQa3VQQ3FOcHI4b2dRR25kMGtpbllwczZKc0tsTVIw?= =?utf-8?B?YkEyRVlvSThOV0dsSTcrcFJOQnZPRzkrZklWdElJQm1TK3lGcUphbVhJa1FH?= =?utf-8?B?ZUE2YWl1S0RKYjlqbWdpelRSQTZ3N0NGd1MzcXJUT2tUNTQwUUFoeWRrQm1M?= =?utf-8?B?VFRqeDQ2RVpmQVdPRzQ3QzVjREZSbmxsdHFaYkpHaTZKYjN3WkdnR0djVmQz?= =?utf-8?B?T2NINDFIWCtOcVVoYnAzU3h0NDczTDZ3R1RxdjJUSEZPajdxTkt5ZnZrNHJi?= =?utf-8?B?YVJHY0xYMWpxaVhyS1YzTmQwWEJQM0dtcThnMWhhNXZXeEg0R1JjSFd4dGRQ?= =?utf-8?B?Z05TbWh3S2Q3eVd3YzJsVlpDR3owL3pocVhtbWRMNkxyUjk1eU9Cb05PcHpm?= =?utf-8?B?T3JLRm1IbDlJUXRrQklLNWJkTFRWcHp4Mk9mQXBJQWNxNEFxcXlDblJIQkx4?= =?utf-8?Q?vdpYgK?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2025 07:10:56.4189 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc7019f1-60ed-495d-8bc7-08ddf1025a6d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7765 From: Carolina Jubran Introduce MLX5_ETH_WQE_FT_META_SHIFT as a shared base offset for features that use the lower 8 bits of the WQE flow_table_metadata field, currently used for timestamping, IPsec, and MACsec. Define MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK so that fs_id occupies bits 2=E2=80=935, making it clear that fs_id occupies bits in the metadata. Set MLX5_ETH_WQE_FT_META_MACSEC_MASK as the OR of the MACsec flag and MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK, corresponding to the original 0x3E mask. Update the fs_id macro to right-shift the MACsec flag by MLX5_ETH_WQE_FT_META_SHIFT and update the RoCE modify-header action to use it. Introduce the helper macro MLX5_MACSEC_TX_METADATA(fs_id) to compose the full shifted MACsec metadata value. These changes make it explicit exactly which metadata bits carry MACsec information, simplifying future feature exclusions when multiple features share the WQE flowtable metadata. In addition, drop the incorrect =E2=80=9CRX flow steering=E2=80=9D comment,= since this applies to TX flow steering. Signed-off-by: Carolina Jubran Reviewed-by: Jianbo Liu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- .../ethernet/mellanox/mlx5/core/en_accel/macsec.c | 2 +- .../ethernet/mellanox/mlx5/core/lib/macsec_fs.c | 12 +++++------- .../ethernet/mellanox/mlx5/core/lib/macsec_fs.h | 15 +++++++++++++++ include/linux/mlx5/qp.h | 9 +++++++-- 4 files changed, 28 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c b/dr= ivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c index 6ab02f3fc291..528b04d4de41 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c @@ -1676,7 +1676,7 @@ void mlx5e_macsec_tx_build_eseg(struct mlx5e_macsec *= macsec, if (!fs_id) return; =20 - eseg->flow_table_metadata =3D cpu_to_be32(MLX5_ETH_WQE_FT_META_MACSEC | f= s_id << 2); + eseg->flow_table_metadata =3D cpu_to_be32(MLX5_MACSEC_TX_METADATA(fs_id)); } =20 void mlx5e_macsec_offload_handle_rx_skb(struct net_device *netdev, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c b/driv= ers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c index 762d55ba9e51..9ec450603176 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c @@ -45,11 +45,7 @@ #define MLX5_SECTAG_HEADER_SIZE_WITHOUT_SCI 0x8 #define MLX5_SECTAG_HEADER_SIZE_WITH_SCI (MLX5_SECTAG_HEADER_SIZE_WITHOUT_= SCI + MACSEC_SCI_LEN) =20 -/* MACsec RX flow steering */ -#define MLX5_ETH_WQE_FT_META_MACSEC_MASK 0x3E - /* MACsec fs_id handling for steering */ -#define macsec_fs_set_tx_fs_id(fs_id) (MLX5_ETH_WQE_FT_META_MACSEC | (fs_i= d) << 2) #define macsec_fs_set_rx_fs_id(fs_id) ((fs_id) | BIT(30)) =20 struct mlx5_sectag_header { @@ -597,7 +593,7 @@ static int macsec_fs_tx_setup_fte(struct mlx5_macsec_fs= *macsec_fs, MLX5_SET(fte_match_param, spec->match_criteria, misc_parameters_2.metadat= a_reg_a, MLX5_ETH_WQE_FT_META_MACSEC_MASK); MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_r= eg_a, - macsec_fs_set_tx_fs_id(id)); + MLX5_MACSEC_TX_METADATA(id)); =20 *fs_id =3D id; flow_act->crypto.type =3D MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC; @@ -2219,8 +2215,10 @@ static int mlx5_macsec_fs_add_roce_rule_tx(struct ml= x5_macsec_fs *macsec_fs, u32 =20 MLX5_SET(set_action_in, action, action_type, MLX5_ACTION_TYPE_SET); MLX5_SET(set_action_in, action, field, MLX5_ACTION_IN_FIELD_METADATA_REG_= A); - MLX5_SET(set_action_in, action, data, macsec_fs_set_tx_fs_id(fs_id)); - MLX5_SET(set_action_in, action, offset, 0); + MLX5_SET(set_action_in, action, data, + mlx5_macsec_fs_set_tx_fs_id(fs_id)); + MLX5_SET(set_action_in, action, offset, + MLX5_ETH_WQE_FT_META_MACSEC_SHIFT); MLX5_SET(set_action_in, action, length, 32); =20 modify_hdr =3D mlx5_modify_header_alloc(mdev, MLX5_FLOW_NAMESPACE_RDMA_TX= _MACSEC, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h b/driv= ers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h index 34b80c3ef6a5..15acaff43641 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h @@ -12,6 +12,21 @@ #define MLX5_MACSEC_METADATA_MARKER(metadata) ((((metadata) >> 30) & 0x3)= =3D=3D 0x1) #define MLX5_MACSEC_RX_METADAT_HANDLE(metadata) ((metadata) & MLX5_MACSEC= _RX_FS_ID_MASK) =20 +/* MACsec TX flow steering */ +#define MLX5_ETH_WQE_FT_META_MACSEC_MASK \ + (MLX5_ETH_WQE_FT_META_MACSEC | MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK) +#define MLX5_ETH_WQE_FT_META_MACSEC_SHIFT MLX5_ETH_WQE_FT_META_SHIFT + +/* MACsec fs_id handling for steering */ +#define mlx5_macsec_fs_set_tx_fs_id(fs_id) \ + (((MLX5_ETH_WQE_FT_META_MACSEC) >> MLX5_ETH_WQE_FT_META_MACSEC_SHIFT) \ + | ((fs_id) << 2)) + +#define MLX5_MACSEC_TX_METADATA(fs_id) \ + (mlx5_macsec_fs_set_tx_fs_id(fs_id) << \ + MLX5_ETH_WQE_FT_META_MACSEC_SHIFT) + +/* MACsec fs_id uses 4 bits, supports up to 16 interfaces */ #define MLX5_MACSEC_NUM_OF_SUPPORTED_INTERFACES 16 =20 struct mlx5_macsec_fs; diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h index 5546c7bd2c83..b21be7630575 100644 --- a/include/linux/mlx5/qp.h +++ b/include/linux/mlx5/qp.h @@ -251,9 +251,14 @@ enum { MLX5_ETH_WQE_SWP_OUTER_L4_UDP =3D 1 << 5, }; =20 +/* Base shift for metadata bits used by timestamping, IPsec, and MACsec */ +#define MLX5_ETH_WQE_FT_META_SHIFT 0 + enum { - MLX5_ETH_WQE_FT_META_IPSEC =3D BIT(0), - MLX5_ETH_WQE_FT_META_MACSEC =3D BIT(1), + MLX5_ETH_WQE_FT_META_IPSEC =3D BIT(0) << MLX5_ETH_WQE_FT_META_SHIFT, + MLX5_ETH_WQE_FT_META_MACSEC =3D BIT(1) << MLX5_ETH_WQE_FT_META_SHIFT, + MLX5_ETH_WQE_FT_META_MACSEC_FS_ID_MASK =3D + GENMASK(5, 2) << MLX5_ETH_WQE_FT_META_SHIFT, }; =20 struct mlx5_wqe_eth_seg { --=20 2.31.1 From nobody Thu Oct 2 20:42:51 2025 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2079.outbound.protection.outlook.com [40.107.100.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2597B26A1AF; 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Miller" , Tariq Toukan , "Mark Bloch" , Sabrina Dubroca , , , , Gal Pressman , Dragos Tatulea , Carolina Jubran , Jianbo Liu Subject: [PATCH mlx5-next 3/3] net/mlx5e: Prevent WQE metadata conflicts between timestamping and offloads Date: Thu, 11 Sep 2025 10:10:19 +0300 Message-ID: <1757574619-604874-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1757574619-604874-1-git-send-email-tariqt@nvidia.com> References: <1757574619-604874-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD4:EE_|SJ5PPFD5E8DE351:EE_ X-MS-Office365-Filtering-Correlation-Id: 3bdc9808-483b-47dd-150f-08ddf1025c41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?rL4z/5p59VZ3/1oL3hLa1inSBWLgLgRh82FXu5Ij8xJlVU4qls5t1HzHuuLn?= =?us-ascii?Q?iR8lspM8tdRUnjc9QQgkqLEmHo+G2a78PmmvRkAG3brZsQLI/DEIPsA1DcpP?= =?us-ascii?Q?XmoWVw3y3rpLtx+5HxxXNivgcLOAA/yVMHvwKL6a5dza7zrfvZxXZwe9048i?= =?us-ascii?Q?5z6E7cxjylYCK6zu5TDfEDaj844qOOpEKiQsZb2AuBbi+kbrXMenJhl7vLt4?= =?us-ascii?Q?xgo+mxQuRylFmXF4ZIt2KRBDCSsl/mtH68NpvB0M3y6cqdmQ1nP/KSa2HpFH?= =?us-ascii?Q?FbYJQJSx7bewl2IFkFTHIdUhKoSqk6S4E5hYhehs95W7IptGdzGwfS1T0xVr?= =?us-ascii?Q?rKP46FjTh3Z0t2D6Kw4RzZ0pS6kkkgjZFowgZgjP9RkvKg+YS5NLuG/fgO8t?= =?us-ascii?Q?vRD0mwOY/GgzfqtAFyGgBN/bKdZ9zQPu4XIhXEjz/JN42XxahlGzXiIZ9XF6?= =?us-ascii?Q?xQ2Xnml/KelF2lV5xRMwgHIp//eVcKa3iE73YG3thVfImnvZtBFq41L3vttI?= =?us-ascii?Q?8zDbtoU81KDzjAzgxpUmJGzuj2PyHNrZntZ/3mMeo3KDmezmW7EnhQTHTetZ?= =?us-ascii?Q?t+i99yguqWBXgHnzV8NjeIEa/GgVskQp9KH3cIo32sKuXwrBmm9J/h5lA1lf?= =?us-ascii?Q?1XIImFsZeqI4kLQ6ca6mHG5FtaDZBiqVxquEoKyln6LkbGeKG31ZqhpS7+Lq?= =?us-ascii?Q?ATTvaaNPj8nSChf8M43DBIYLUGLjyBtkUZJeGwAwfM/Z2n3+yI+VSxlRGXQl?= =?us-ascii?Q?0qXezjc+ZbacVAykXvtoDv4t1+v4sJ4zaOhBObptuXFIvTA4MUQ97PJd9n1y?= =?us-ascii?Q?IZGaNbqGk8GL+sNGFkBFmr1j0F5sN6rC6C/2Lsa2aHAB8Tj4FZHIUNQCzzc2?= =?us-ascii?Q?yVtaWeNMfN2o2eK02d1hW6oYyh70Dfv8k2grpt5zXEbUyAS4VNK06pxmNF7a?= =?us-ascii?Q?99M2UuojbwANnHUR1H5LURBYjp9L2rI7j7nPGUANhxhB9tYS46j2OEIuxHZK?= =?us-ascii?Q?I5X27hwUgDGhjdCAmxUJhTYQikKlFcG85l7vCqNFiS5koZGjSGUmtvsAQ6uq?= =?us-ascii?Q?HjNJYf/YuP7AthkSrOCKcRXVr7+8aWoExpMyWyMz664TM1ORfpMeFg9b7alF?= =?us-ascii?Q?1BpuFhPuay6mysBGjThlBtRD7iOCoGHkRg95jKNcCgrxt0h4E1T9sn4IcO8o?= =?us-ascii?Q?K3Bf5afA1V3IjyykXnZVzoXAhA+RRA4CARzTsOcnJ1LnewtNeN5dCvryzjDO?= =?us-ascii?Q?Hi/aHrBSuOpVwBljH0jiyp+C05S7jNAdPa7T+K/j9DI/rQ62UX6gIfGsiTrN?= =?us-ascii?Q?7fQTgWqCooX6aYPbv7gFu39r7JVr84M/ZeHQkMvyEJVu9e79Zr4mdxMNtolg?= =?us-ascii?Q?JHEsBvAT5dUPpRfQIJTObHGfXP8ete7jclWGZSWyHoweS5oKrxky2/fb9K4d?= =?us-ascii?Q?StqXRr+B37Ork9qBT9svmyzq+j5tmMNOAg8ML/LLrFt08e/cUsHHzvoGklyB?= =?us-ascii?Q?Ty6SDUXc//HJx6NBUZSuCKqcKRHCqny4Cs9f?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2025 07:10:59.4613 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bdc9808-483b-47dd-150f-08ddf1025c41 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPFD5E8DE351 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Update the WQE metadata assignment to avoid overriding existing metadata when setting the sysport timestamp ID. Since timestamp IDs are limited to 256 values, they use only the lower 8 bits of the metadata field. To avoid conflicts, move IPsec and MACsec metadata ID to bits 8 and 9, and shift the MACsec fs_id accordingly. This ensures safe coexistence of timestamping and offload features that use the same metadata field. Signed-off-by: Carolina Jubran Reviewed-by: Jianbo Liu Reviewed-by: Patrisious Haddad Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/en_tx.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c | 2 +- include/linux/mlx5/qp.h | 5 +++-- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_tx.c index 319061d31602..6c55b67b7335 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c @@ -653,7 +653,7 @@ static void mlx5e_cqe_ts_id_eseg(struct mlx5e_ptpsq *pt= psq, struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg) { if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) - eseg->flow_table_metadata =3D + eseg->flow_table_metadata |=3D cpu_to_be32(mlx5e_ptp_metadata_fifo_peek(&ptpsq->metadata_freelist)); } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c b/driv= ers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c index 9ec450603176..e6be2f01daf4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c @@ -2219,7 +2219,7 @@ static int mlx5_macsec_fs_add_roce_rule_tx(struct mlx= 5_macsec_fs *macsec_fs, u32 mlx5_macsec_fs_set_tx_fs_id(fs_id)); MLX5_SET(set_action_in, action, offset, MLX5_ETH_WQE_FT_META_MACSEC_SHIFT); - MLX5_SET(set_action_in, action, length, 32); + MLX5_SET(set_action_in, action, length, 8); =20 modify_hdr =3D mlx5_modify_header_alloc(mdev, MLX5_FLOW_NAMESPACE_RDMA_TX= _MACSEC, 1, action); diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h index b21be7630575..d67aedc6ea68 100644 --- a/include/linux/mlx5/qp.h +++ b/include/linux/mlx5/qp.h @@ -251,8 +251,9 @@ enum { MLX5_ETH_WQE_SWP_OUTER_L4_UDP =3D 1 << 5, }; =20 -/* Base shift for metadata bits used by timestamping, IPsec, and MACsec */ -#define MLX5_ETH_WQE_FT_META_SHIFT 0 +/* Metadata bits 0-7 are used by timestamping */ +/* Base shift for metadata bits used by IPsec and MACsec */ +#define MLX5_ETH_WQE_FT_META_SHIFT 8 =20 enum { MLX5_ETH_WQE_FT_META_IPSEC =3D BIT(0) << MLX5_ETH_WQE_FT_META_SHIFT, --=20 2.31.1