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Wed, 10 Sep 2025 03:25:29 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jiri Pirko , Jonathan Corbet , "Leon Romanovsky" , Jason Gunthorpe , Saeed Mahameed , Tariq Toukan , Mark Bloch , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , "John Fastabend" , , , , , , Gal Pressman , Cosmin Ratiu , Dragos Tatulea , Jiri Pirko Subject: [PATCH net-next 05/10] net/mlx5e: Prepare for using multiple TX doorbells Date: Wed, 10 Sep 2025 13:24:46 +0300 Message-ID: <1757499891-596641-6-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1757499891-596641-1-git-send-email-tariqt@nvidia.com> References: <1757499891-596641-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F0:EE_|DS7PR12MB6006:EE_ X-MS-Office365-Filtering-Correlation-Id: eaf4e50e-17d6-4159-59bb-08ddf054711c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?6WnsRexnj6L3J88B/cvAJHxdddUDOqGozg+ny404zLlcZ90VShQQz5nFPU/5?= =?us-ascii?Q?B2KtQd0gROZejclf87MmCSGuX/N5Q4tLkO+7lbTDdG2f9SWHUsB7NDUiinXL?= =?us-ascii?Q?0WG0SI1Dtca6smbCaOIRFAJEDQFV7dKC6bBweOW9NKBxRUF899pvEtrUUL9E?= =?us-ascii?Q?ey0Pl21FnqONazgPiNTuCbsIq9AB0Yr4CmkiDVPYdlV/uUsRWtIW6FMnmkFi?= =?us-ascii?Q?DbReMOFc7humHmrTQC1a3lxMmHTqOJ4r3xg7OF2/cY9v/isURpdi4HDKbZ7p?= =?us-ascii?Q?ehVyVZUbmZzI6l8sh7RHciYiaLv4oOyvDckiKKDYQAo/lKgrFnDTB1Lp1z60?= =?us-ascii?Q?zqVmJ3+p/Zyy0oW5gtEWSFy3+YFiUBvMvsCX6bvbVBHi6r8W/TxXZcSz2wt6?= =?us-ascii?Q?/OLgoBbcDl2xPhfiH3shbpkHJZF4sbEGMMs+9ffFL7mcCh+XIW3OKSZAz/+5?= =?us-ascii?Q?TP3QJzxqwKJxYu2zpnq/d2oNkcNZH9Q+7WY1wcI1sCOvHRwQMexil8YaMjWQ?= =?us-ascii?Q?jCXI6honln18b+3rk8tMYkENw5XkWOPtVID/Y9KdLVmHGnrBZSw1viWK2Bf7?= =?us-ascii?Q?3nKw4wWzZriK1+3rQuq7pQFz3qgTZkpdOs2Q1yi5HIXTzZikpph8Cq0G/AW7?= =?us-ascii?Q?54LrACGb0jWzKf9dA8ZERBLi3Zx+svLrSBmgvp6z3Mdv79V0jKhx6OcLCbyp?= =?us-ascii?Q?4KtHZWRtSjx0Q//8SoIxNa6EDjjB2OzO4SEu1/DY56IL4bAB5FMQYlaXsjR5?= =?us-ascii?Q?02l64pgPZtmb1zdscw3Ymo53VqxgX80D/hG3mHHQqOwthBLr8MazNVFC/ibr?= =?us-ascii?Q?h8T78ClKGqbLcKVuDR3fr6FWs6hr8ztgORL9N8i9siqjv95G2Q9lnwmmxvto?= =?us-ascii?Q?Ez1NZsmuIksnv5ZqXFOogbC7cT7wRvhetYyQGttv5F7AcsMs0ezG8/5kmm/F?= =?us-ascii?Q?KuWlCHF1MHYLt/hOxcOT3ANRCvz/wU/+qrAgDREdvalflKESKsIlZ0iwNMSL?= =?us-ascii?Q?DVtLo6Oxw5Hg0WrQQ8ml6MncXXRcqUOAoOr9yNj7esAjNUHFyKZwRLrYFg40?= =?us-ascii?Q?zV6jalWkcLxcTNN3Ptc4CTyjKZulJYPoggOvFJu0TfC9LolP+xXKa98UFJZs?= =?us-ascii?Q?jCYnT7JWB0BiA3SRn4dTKLxqfk3fIZ5E/ThSeMG57VBQ/sM6/mVToqRIU0FJ?= =?us-ascii?Q?Cg6+SDlZiYvWy15c00TDi8Xee6mTf29Ef/ed8Xf8IlY7uiPoXrPwjtM342g4?= =?us-ascii?Q?z9ECjgLvjF57pepoAM8IP/BhGsDXbvg2b5FNjpqZs1aZmg/AnuSuj5cyfD7c?= =?us-ascii?Q?uQOzL/4sEEjzHiFv5r1w8rXI4xLggMOlOEtyed3NIhBDl6UIdY/pQDRJUSR4?= =?us-ascii?Q?laZR9+QWkFHwsQgv22yJ9WHCeSzv6GrhQQsxY5DGO88dcaAs6D5+8FBoVLau?= =?us-ascii?Q?zSXKuQ49s9qzzu2hCVLqh8RwxK3NQqt+e8v5Wu9MgSCQhItXKzcF07+ETWQG?= =?us-ascii?Q?cfgHTPhf12n2hNwIlUEVKXsM+/EWdBX8C2a+?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2025 10:26:01.9541 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eaf4e50e-17d6-4159-59bb-08ddf054711c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6006 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu The driver allocates a single doorbell per device and uses it for all Send Queues (SQs). This can become a bottleneck due to the high number of concurrent MMIO accesses when ringing the same doorbell from many channels. This patch makes the doorbells used by channel queues configurable. mlx5e_channel_pick_doorbell() is added to select the doorbell to be used for a given channel, picking the default for now. When opening a channel, the selected doorbell is saved to the channel struct and used whenever channel-related queues are created. Finally, 'uar_page' is added to 'struct mlx5e_create_sq_param' to control which doorbell to use when allocating an SQ, since that can happen outside channel context (e.g. for PTP). Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + .../ethernet/mellanox/mlx5/core/en/params.h | 1 + .../net/ethernet/mellanox/mlx5/core/en/ptp.c | 4 +++- .../net/ethernet/mellanox/mlx5/core/en/ptp.h | 1 + .../net/ethernet/mellanox/mlx5/core/en_main.c | 18 ++++++++++++++---- 5 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 0dd3bc0f4caa..9c73165653bf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -788,6 +788,7 @@ struct mlx5e_channel { int vec_ix; int sd_ix; int cpu; + struct mlx5_sq_bfreg *bfreg; /* Sync between icosq recovery and XSK enable/disable. */ struct mutex icosq_recovery_lock; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.h index e3edf79dde5f..00617c65fe3c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h @@ -51,6 +51,7 @@ struct mlx5e_create_sq_param { u32 tisn; u8 tis_lst_sz; u8 min_inline_mode; + u32 uar_page; }; =20 /* Striding RQ dynamic parameters */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/ptp.c index 7c1d9a9ea464..a392578a063c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c @@ -334,7 +334,7 @@ static int mlx5e_ptp_alloc_txqsq(struct mlx5e_ptp *c, i= nt txq_ix, sq->mdev =3D mdev; sq->ch_ix =3D MLX5E_PTP_CHANNEL_IX; sq->txq_ix =3D txq_ix; - sq->uar_map =3D mdev->priv.bfreg.map; + sq->uar_map =3D c->bfreg->map; sq->min_inline_mode =3D params->tx_min_inline_mode; sq->hw_mtu =3D MLX5E_SW2HW_MTU(params, params->sw_mtu); sq->stats =3D &c->priv->ptp_stats.sq[tc]; @@ -486,6 +486,7 @@ static int mlx5e_ptp_open_txqsq(struct mlx5e_ptp *c, u3= 2 tisn, csp.wq_ctrl =3D &txqsq->wq_ctrl; csp.min_inline_mode =3D txqsq->min_inline_mode; csp.ts_cqe_to_dest_cqn =3D ptpsq->ts_cq.mcq.cqn; + csp.uar_page =3D c->bfreg->index; =20 err =3D mlx5e_create_sq_rdy(c->mdev, sqp, &csp, 0, &txqsq->sqn); if (err) @@ -900,6 +901,7 @@ int mlx5e_ptp_open(struct mlx5e_priv *priv, struct mlx5= e_params *params, c->num_tc =3D mlx5e_get_dcb_num_tc(params); c->stats =3D &priv->ptp_stats.ch; c->lag_port =3D lag_port; + c->bfreg =3D &mdev->priv.bfreg; =20 err =3D mlx5e_ptp_set_state(c, params); if (err) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/ptp.h index 883c044852f1..1b3c9648220b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h @@ -66,6 +66,7 @@ struct mlx5e_ptp { struct mlx5_core_dev *mdev; struct hwtstamp_config *tstamp; DECLARE_BITMAP(state, MLX5E_PTP_STATE_NUM_STATES); + struct mlx5_sq_bfreg *bfreg; }; =20 static inline bool mlx5e_use_ptpsq(struct sk_buff *skb) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 02a538ec2ecb..0425f0e3d3a0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -1532,7 +1532,7 @@ static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, sq->pdev =3D c->pdev; sq->mkey_be =3D c->mkey_be; sq->channel =3D c; - sq->uar_map =3D mdev->priv.bfreg.map; + sq->uar_map =3D c->bfreg->map; sq->min_inline_mode =3D params->tx_min_inline_mode; sq->hw_mtu =3D MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN; sq->xsk_pool =3D xsk_pool; @@ -1617,7 +1617,7 @@ static int mlx5e_alloc_icosq(struct mlx5e_channel *c, int err; =20 sq->channel =3D c; - sq->uar_map =3D mdev->priv.bfreg.map; + sq->uar_map =3D c->bfreg->map; sq->reserved_room =3D param->stop_room; =20 param->wq.db_numa_node =3D cpu_to_node(c->cpu); @@ -1702,7 +1702,7 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, sq->priv =3D c->priv; sq->ch_ix =3D c->ix; sq->txq_ix =3D txq_ix; - sq->uar_map =3D mdev->priv.bfreg.map; + sq->uar_map =3D c->bfreg->map; sq->min_inline_mode =3D params->tx_min_inline_mode; sq->hw_mtu =3D MLX5E_SW2HW_MTU(params, params->sw_mtu); sq->max_sq_mpw_wqebbs =3D mlx5e_get_max_sq_aligned_wqebbs(mdev); @@ -1778,7 +1778,7 @@ static int mlx5e_create_sq(struct mlx5_core_dev *mdev, MLX5_SET(sqc, sqc, flush_in_error_en, 1); =20 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); - MLX5_SET(wq, wq, uar_page, mdev->priv.bfreg.index); + MLX5_SET(wq, wq, uar_page, csp->uar_page); MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma); @@ -1882,6 +1882,7 @@ int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tis= n, int txq_ix, csp.cqn =3D sq->cq.mcq.cqn; csp.wq_ctrl =3D &sq->wq_ctrl; csp.min_inline_mode =3D sq->min_inline_mode; + csp.uar_page =3D c->bfreg->index; err =3D mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq= ->sqn); if (err) goto err_free_txqsq; @@ -2052,6 +2053,7 @@ static int mlx5e_open_icosq(struct mlx5e_channel *c, = struct mlx5e_params *params csp.cqn =3D sq->cq.mcq.cqn; csp.wq_ctrl =3D &sq->wq_ctrl; csp.min_inline_mode =3D params->tx_min_inline_mode; + csp.uar_page =3D c->bfreg->index; err =3D mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); if (err) goto err_free_icosq; @@ -2112,6 +2114,7 @@ int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct = mlx5e_params *params, csp.cqn =3D sq->cq.mcq.cqn; csp.wq_ctrl =3D &sq->wq_ctrl; csp.min_inline_mode =3D sq->min_inline_mode; + csp.uar_page =3D c->bfreg->index; set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); =20 err =3D mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); @@ -2740,6 +2743,11 @@ void mlx5e_trigger_napi_sched(struct napi_struct *na= pi) local_bh_enable(); } =20 +static void mlx5e_channel_pick_doorbell(struct mlx5e_channel *c) +{ + c->bfreg =3D &c->mdev->priv.bfreg; +} + static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, struct mlx5e_params *params, struct xsk_buff_pool *xsk_pool, @@ -2794,6 +2802,8 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv= , int ix, c->aff_mask =3D irq_get_effective_affinity_mask(irq); c->lag_port =3D mlx5e_enumerate_lag_port(mdev, ix); =20 + mlx5e_channel_pick_doorbell(c); + netif_napi_add_config_locked(netdev, &c->napi, mlx5e_napi_poll, ix); netif_napi_set_irq_locked(&c->napi, irq); =20 --=20 2.31.1