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Sun, 7 Sep 2025 02:40:48 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Jonathan Corbet" , Jiri Pirko , , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net-next 2/2] net/mlx5e: Add stale counter for PCIe congestion events Date: Sun, 7 Sep 2025 12:39:36 +0300 Message-ID: <1757237976-531416-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1757237976-531416-1-git-send-email-tariqt@nvidia.com> References: <1757237976-531416-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000145:EE_|SA1PR12MB7224:EE_ X-MS-Office365-Filtering-Correlation-Id: 590f5178-8347-44a1-0916-08ddedf2a7ca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Qba3o5DYH/HguBkE44m4tvlWh3ushsHIT3EUlYCMVjnUPGZo28y7WGuorKZm?= =?us-ascii?Q?Wwd2ujA631Cvdq5D7RjpXF7atjpTjiO1fvsLmkyfjqft4mbT/ZUbavuT3ZpV?= =?us-ascii?Q?zZgxdQDomsP4R4BeDdweo2aYIkGqp0aV/hd9wiuQgB0FN7KbzWdgq1MnmF3B?= =?us-ascii?Q?0Qb52LkDleB8XUoDhqYUBvt+jncfJoFoOCZC/GoRnQgY6rr5pn82LNWsnwTC?= =?us-ascii?Q?hityw4V0SSZOlYrHrcrW9goTpvSeLsgxmRxnVBe6CuATrgs2xf39xldKwSQ8?= =?us-ascii?Q?kH3SGXxaTYg5EL1rP4H1PVYZfErF/0QgY7GVMtf8yZgtgtXnouSrJG1YrNI8?= =?us-ascii?Q?EOYtIGjMMtR9MMY/ZHRr/MKyWjKgs4Ids9+/5hnskjl+6hBV71YutAZGsA6K?= =?us-ascii?Q?VhQpmIoPrtSEVE3uVAlMWsRdABEABMrIZxcjcMxmhRQmpNGfVoeHB/rq+cEp?= =?us-ascii?Q?JNqDLCgvdtrMM2j5L4F9TNpQTHh69h4g4Elw3pWiTwKsrEdlLXqtDfFV8CkC?= =?us-ascii?Q?zS/9LYR5MOZj3FcWBuZy4pHxTTLIpIFuJqK0Dp1cjlTXtaTDp7hfkY8mW60t?= =?us-ascii?Q?/4k8KPBq+MndAqMu8YqxUzYvl5/f60O5jX+FwPV3DZtLSnvvN4AkA6avJpPD?= =?us-ascii?Q?IAd4F9vEjVm6+Y82C037/DaQoY7RUgldfYyB6b3h2VJF41l5IJXVQ9DLDsmv?= =?us-ascii?Q?VTYC9tq3LF44g/QTFNRN0mR/Yi8cvZjej7KaB2V41IyaYsjmplp4fWzbYCOA?= =?us-ascii?Q?0/nXKQkrr4DMxhMWqb08Yl4+csdGVhsjRm4dvGC544Fn3mvH9Zgc0FkDJE++?= =?us-ascii?Q?HLeHFwUL8CbXuXwweXDH5JPPcfeMoNYj5SkaRyyciqXRSX7ZnfVgtn/Dhf1X?= =?us-ascii?Q?M4thBN2ZDQqdGz0PpIkux08FpeJ01/HRPRC4BtQupO7XA9LKJcPOGayALpjx?= =?us-ascii?Q?Qd6x1zIRT7B3HsTB1RSWozmK0yMYbCq0S2t+9bcEkfRIUzKcEsGKEacfRI+o?= =?us-ascii?Q?GZsktMpQfGz3HcfjjVVgSIvR74LWpHbjlDIxLQaiF+fDELtKOxomKSsuwHlJ?= =?us-ascii?Q?Sa86zWnweLqWVAs/lx67rQhiq9UE3DrJ2/iMhpH/W3auC8/0VK4wCKh+yB9T?= =?us-ascii?Q?paLEvzR3gfYHCNnvlcMFRpKH3AYpJCqCMM2LOFYV7qO4V4vUZXAZM4feWiaB?= =?us-ascii?Q?eZNz+T275U+G1lW3FJWFmwv9k96cR9iAwY19GM7d8rKwW5wpTr2pRpjlQ/FN?= =?us-ascii?Q?y0xsCqP9+SF55w4fN5JiIjuPS/h49OoDIdWvT3gR9f1kdyh78EQA1iWHrht/?= =?us-ascii?Q?eRta5KbecGPKmFTAJZ4yIZxOEj04u/g+yqBz2etchQaoCcz8KDTX5UQD8mIL?= =?us-ascii?Q?viWN6uLV5f8r2zHuBY/QyBCah+pKBS2ifUQrWwMxdjAw/bwN/tJ3lZM/AzYm?= =?us-ascii?Q?RdXU8Hdq4X7hjK5Hhml0/vnDGd352FrIMFNNaUxCPrVbpq5lAZJyJ22qg2cr?= =?us-ascii?Q?Tevo6iYW7dtCjrZJy6XWQjrOt/YtAIPuFpJn?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2025 09:41:00.7906 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 590f5178-8347-44a1-0916-08ddedf2a7ca X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000145.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7224 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea This ethtool counter is meant to help with observing how many times the congestion event was triggered but on query there was no state change. This would help to indicate when a work item was scheduled to run too late and in the meantime the congestion state changed back to previous state. While at it, do a driveby typo fix in documentation for pci_bw_inbound_high. Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../device_drivers/ethernet/mellanox/mlx5/counters.rst | 7 ++++++- .../net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c | 7 ++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5= /counters.rst b/Documentation/networking/device_drivers/ethernet/mellanox/m= lx5/counters.rst index 754c81436408..cc498895f92e 100644 --- a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counte= rs.rst +++ b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counte= rs.rst @@ -1348,7 +1348,7 @@ Device Counters is in a congested state. If pci_bw_inbound_high =3D=3D pci_bw_inbound_low then the device is= not congested. If pci_bw_inbound_high > pci_bw_inbound_low then the device is cong= ested. - - Tnformative + - Informative =20 * - `pci_bw_inbound_low` - The number of times the device crossed the low inbound PCIe bandwid= th @@ -1373,3 +1373,8 @@ Device Counters If pci_bw_outbound_high =3D=3D pci_bw_outbound_low then the device = is not congested. If pci_bw_outbound_high > pci_bw_outbound_low then the device is co= ngested. - Informative + + * - `pci_bw_stale_event` + - The number of times the device fired a PCIe congestion event but on= query + there was no change in state. + - Informative diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c b= /drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c index 0cf142f71c09..2eb666a46f39 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c @@ -24,6 +24,7 @@ struct mlx5e_pcie_cong_stats { u32 pci_bw_inbound_low; u32 pci_bw_outbound_high; u32 pci_bw_outbound_low; + u32 pci_bw_stale_event; }; =20 struct mlx5e_pcie_cong_event { @@ -52,6 +53,8 @@ static const struct counter_desc mlx5e_pcie_cong_stats_de= sc[] =3D { pci_bw_outbound_high) }, { MLX5E_DECLARE_STAT(struct mlx5e_pcie_cong_stats, pci_bw_outbound_low) }, + { MLX5E_DECLARE_STAT(struct mlx5e_pcie_cong_stats, + pci_bw_stale_event) }, }; =20 #define NUM_PCIE_CONG_COUNTERS ARRAY_SIZE(mlx5e_pcie_cong_stats_desc) @@ -212,8 +215,10 @@ static void mlx5e_pcie_cong_event_work(struct work_str= uct *work) } =20 changes =3D cong_event->state ^ new_cong_state; - if (!changes) + if (!changes) { + cong_event->stats.pci_bw_stale_event++; return; + } =20 cong_event->state =3D new_cong_state; =20 --=20 2.31.1