From nobody Wed Sep 10 11:00:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BE98306B1D; Fri, 5 Sep 2025 14:58:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757084307; cv=none; b=lqsFmd14p5XVf4hM7B4YsjC8JT3w98vnkr8deVqY+94zEk9fUf0EPeQnfPJYzbjOKhuGpylPqhD6XAdZneEbPZVplMTCZU8Aspru/n2X2PwLVptD1MnnjlPH9dSPJw5viBxVG6q4pMZX73mB1W/DkqkM88THU/AOJ0nw0/jsH5Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757084307; c=relaxed/simple; bh=u2SnMniYqIdTGMz3VmsvHD4YSv0VfLGBYGvO+y0pNYU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YW9chzuV/V1Xewr65gb59jaACVdrQtwAFZX+z3XFQVGzbTS0PW3eelcKUXs4h8zoK+/9trprehz2S2zD3SUy3Za+o0POUockpyZabKz2tPX1UbVCEERU7wnWPhB9a/a0H6ppjZj19OHcqigv6LZOcVbjaf89+hxe6rIKFGgMOBk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=j6fatnkG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="j6fatnkG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EC101C4CEF1; Fri, 5 Sep 2025 14:58:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757084306; bh=u2SnMniYqIdTGMz3VmsvHD4YSv0VfLGBYGvO+y0pNYU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j6fatnkGBPB+79JlcIDN/NOow/R8Hu4RM7TCm4idjTODgKVQ7KOOU35927qBCtvys Qb4giQ1tDXN2c00OulbSsy8qAgftreaVCyP4FjPDPJJojArs5V39+M96pDA7WxKgpf 9LajZWAGG0ed3QxD3NIm3y5QZjSjYfxCRth++Vq03Nkm4+l6P+hcGQmxXQR3kqW6rM eUqlTeugjwH+qLuziOH6QlWDOqNVt3SRsRpvDr4EaUCLXhTrUTl3M+fLhI1krdH1Xd HY+6fkPUDe85I4AJas2pEYc0Mm7fE8FdbvZQWqDP505itN+baCwt0kTH63oCPDcGbM /I/OcwAVW4+CA== From: "Masami Hiramatsu (Google)" To: Steven Rostedt , Peter Zijlstra , Ingo Molnar , x86@kernel.org Cc: Jinchao Wang , Mathieu Desnoyers , Masami Hiramatsu , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , Alexander Shishkin , Ian Rogers , linux-kernel@vger.kernel.org, linux-trace-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: [PATCH v2 2/6] x86/HWBP: introduce arch_reinstall_hw_breakpoint() for atomic context Date: Fri, 5 Sep 2025 23:58:20 +0900 Message-ID: <175708430003.64001.2912914200195124153.stgit@devnote2> X-Mailer: git-send-email 2.43.0 In-Reply-To: <175708427997.64001.11661389635019507808.stgit@devnote2> References: <175708427997.64001.11661389635019507808.stgit@devnote2> User-Agent: StGit/0.19 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Jinchao Wang Introduce arch_reinstall_hw_breakpoint() to update hardware breakpoint parameters (address, length, type) without freeing and reallocating the debug register slot. This allows atomic updates in contexts where memory allocation is not permitted, such as kprobe handlers. Signed-off-by: Jinchao Wang --- arch/x86/include/asm/hw_breakpoint.h | 1 + arch/x86/kernel/hw_breakpoint.c | 50 ++++++++++++++++++++++++++++++= ++++ 2 files changed, 51 insertions(+) diff --git a/arch/x86/include/asm/hw_breakpoint.h b/arch/x86/include/asm/hw= _breakpoint.h index 0bc931cd0698..bb7c70ad22fe 100644 --- a/arch/x86/include/asm/hw_breakpoint.h +++ b/arch/x86/include/asm/hw_breakpoint.h @@ -59,6 +59,7 @@ extern int hw_breakpoint_exceptions_notify(struct notifie= r_block *unused, =20 =20 int arch_install_hw_breakpoint(struct perf_event *bp); +int arch_reinstall_hw_breakpoint(struct perf_event *bp); void arch_uninstall_hw_breakpoint(struct perf_event *bp); void hw_breakpoint_pmu_read(struct perf_event *bp); void hw_breakpoint_pmu_unthrottle(struct perf_event *bp); diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoin= t.c index b01644c949b2..89135229ed21 100644 --- a/arch/x86/kernel/hw_breakpoint.c +++ b/arch/x86/kernel/hw_breakpoint.c @@ -132,6 +132,56 @@ int arch_install_hw_breakpoint(struct perf_event *bp) return 0; } =20 +/* + * Reinstall a hardware breakpoint on the current CPU. + * + * This function is used to re-establish a perf counter hardware breakpoin= t. + * It finds the debug address register slot previously allocated for the + * breakpoint and re-enables it by writing the address to the debug regist= er + * and setting the corresponding bits in the debug control register (DR7). + * + * It is expected that the breakpoint's event context lock is already held + * and interrupts are disabled, ensuring atomicity and safety from other + * event handlers. + */ +int arch_reinstall_hw_breakpoint(struct perf_event *bp) +{ + struct arch_hw_breakpoint *info =3D counter_arch_bp(bp); + unsigned long *dr7; + int i; + + lockdep_assert_irqs_disabled(); + + for (i =3D 0; i < HBP_NUM; i++) { + struct perf_event **slot =3D this_cpu_ptr(&bp_per_reg[i]); + + if (*slot =3D=3D bp) + break; + } + + if (WARN_ONCE(i =3D=3D HBP_NUM, "Can't find a matching breakpoint slot")) + return -EINVAL; + + set_debugreg(info->address, i); + __this_cpu_write(cpu_debugreg[i], info->address); + + dr7 =3D this_cpu_ptr(&cpu_dr7); + *dr7 |=3D encode_dr7(i, info->len, info->type); + + /* + * Ensure we first write cpu_dr7 before we set the DR7 register. + * This ensures an NMI never see cpu_dr7 0 when DR7 is not. + */ + barrier(); + + set_debugreg(*dr7, 7); + if (info->mask) + amd_set_dr_addr_mask(info->mask, i); + + return 0; +} +EXPORT_SYMBOL_GPL(arch_reinstall_hw_breakpoint); + /* * Uninstall the breakpoint contained in the given counter. *