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Wed, 3 Sep 2025 00:30:26 -0700 From: Tariq Toukan To: Saeed Mahameed , Leon Romanovsky CC: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , Tariq Toukan , "Mark Bloch" , , , , Gal Pressman , Vadim Fedorenko , Dragos Tatulea , Carolina Jubran , Yael Chemla Subject: [PATCH mlx5-next] net/mlx5: Add RS FEC histogram infrastructure Date: Wed, 3 Sep 2025 10:30:00 +0300 Message-ID: <1756884600-520195-1-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003447:EE_|LV8PR12MB9692:EE_ X-MS-Office365-Filtering-Correlation-Id: a5437311-f15e-420f-32ae-08ddeabbd905 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?jFFpAODDaOiaiKK+nvATXh0+tYvsQ/evHnXNMkysRa2/C2QEXnjZxv7Zlffb?= =?us-ascii?Q?/DXwNeISJssDs+PT0oiR77eDcwBRuiIgKV1OO1j3w2cBT8ihw1ebMHom5ycc?= =?us-ascii?Q?Syi4lWrzkBB6QMc9hgmuS/JcAWvxvW99CkXok8apAi3Nt9QgP3dMUJS4H1JN?= =?us-ascii?Q?rNbNH97aGNNJIgMElcIp8QLvbXdpymscZC37uJc8ykZAlv1RiH/DpW5Ua4K2?= =?us-ascii?Q?hb6QU58QFkimi357l/9FWq50dlLfe7y4vuFQFIjNaNBge664dcZjkeaTi5WM?= =?us-ascii?Q?OGfXG2WYF6CfsnZVjETeChjsER3hkscqIsYRjQ+W18Xd0XPKLZr6DowhWR/h?= =?us-ascii?Q?2i+uk8VKcAhs0FcJGKOBnCN6lMcaT18WGC9aaX2ZhRbSitXAigJyJ7dP+0Zj?= =?us-ascii?Q?/r88jLLit5pnMk3kDRbyLdXY9vt3frW7PDGImK4xFvSmJeLGa65e9kFHANCl?= =?us-ascii?Q?gHKsmo5qP/MRhjrAdTIWYB9V84CIUH0lCenHc3FZeGWw29yNSVXnr3VUmjE9?= =?us-ascii?Q?TdHPDENT/snSaZATvJb4iHq4OF5DZMNA+RVxBAdsuthV8jrcrryylZmu1T6I?= =?us-ascii?Q?RVFxZA0wZy+K1blv08yCRWxaWYPURZhi+3PWvf5EbvSnDSSpmajUio7r6YQT?= =?us-ascii?Q?Yrty2eVqvqFYSvBvDRjYww5s0/eZeIWR30Y9CclsIH1NiUQWk0mT4i4BBQm5?= =?us-ascii?Q?BW2yenjHbAhjLsz4crFYsdeIz4G9sM6L/G2O4mPhSnwaSHTWaoMYlp2DI/32?= =?us-ascii?Q?Se/GuBspF/wDu/sGlX/13MocTP5R71SuaoYn6t6TE32qMjLc5C+xYeI7kSHf?= =?us-ascii?Q?BJzLMDvW/t6NKjicliRMGMHd4Qd4WmD9AdMNfTd44ekV+ZxGIC2PSnIvYEjk?= =?us-ascii?Q?l8Coe2kdImVMWEIyhYPjc54T9Sk8T0efCBlK2XhUVcT6Q08+kLGtx6nWOksz?= =?us-ascii?Q?MvbBha5Rb7ivPRdF9KLxDZzGFGAkxSx2jl0CPANr3MBT6AA6Mk8kDpFgfRcb?= =?us-ascii?Q?ql8IH/NA9t6ohqRk70KFsWykyNF9Q+nGkUQKsFpMstvUWGCkNWnYQx8Hfkmm?= =?us-ascii?Q?qwa3uusOg+2xijzbniJlQEDeixWfobK8Uim1mvU7+TGEwgAAEZbCgnz8jJAy?= =?us-ascii?Q?xFh8QeZ6cy0wfgR8kG668N9mQEh3NXdGk5oUNbnbuMdKBWEwXsk3i5wCVan4?= =?us-ascii?Q?DkmCsVyvJjPDoQTMxG9HXezQy35uk7f8BjjbVGW7uvElzOWcCAbXx3tYPmjR?= =?us-ascii?Q?NOK9tHmQRHH85fFcx37Bs6YpO3kMJ7ZxEz8kfFVZmbYULmfB5cweHJp0D+sd?= =?us-ascii?Q?u/GFe/DgC1P1yMiGB3fOEWSG5Veyyzu2jCR/TSOXgSkzR3v+tXpi/sMpKLeX?= =?us-ascii?Q?yemhbzEAz1epzQmetEpbgK57LoJJ4MzfDIpCkzhzN9G0L3oGmAU6CoSgMD0v?= =?us-ascii?Q?NM9Nmqqj6vRzkbvXiATBTek+AGxwqedH9iq8fLda/nhvuwK1Ss3wLAJo2s/N?= =?us-ascii?Q?6WTIlrBlmlLGCvgyZ7Cxk0vlAn+R9BdbTBdA?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Sep 2025 07:31:07.5858 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5437311-f15e-420f-32ae-08ddeabbd905 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003447.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9692 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Define the Ports Phy Histogram Configuration Register (PPHCR) to expose RS-FEC histogram bin ranges, and expose a new counter group in the Ports Performance Counters Register (PPCNT) to report the corresponding histogram values. Co-developed-by: Yael Chemla Signed-off-by: Yael Chemla Signed-off-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- include/linux/mlx5/device.h | 1 + include/linux/mlx5/driver.h | 1 + include/linux/mlx5/mlx5_ifc.h | 29 +++++++++++++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index 72a83666e67f..d7f46a8fbfa1 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1525,6 +1525,7 @@ enum { MLX5_PHYSICAL_LAYER_RECOVERY_GROUP =3D 0x1a, MLX5_INFINIBAND_PORT_COUNTERS_GROUP =3D 0x20, MLX5_INFINIBAND_EXTENDED_PORT_COUNTERS_GROUP =3D 0x21, + MLX5_RS_FEC_HISTOGRAM_GROUP =3D 0x23, }; =20 enum { diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 8c5fbfb85749..c0858af0e854 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -130,6 +130,7 @@ enum { MLX5_REG_PDDR =3D 0x5031, MLX5_REG_PMLP =3D 0x5002, MLX5_REG_PPLM =3D 0x5023, + MLX5_REG_PPHCR =3D 0x503E, MLX5_REG_PCAM =3D 0x507f, MLX5_REG_NODE_DESC =3D 0x6001, MLX5_REG_HOST_ENDIANNESS =3D 0x7004, diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index e9f14a0c7f4f..097b1b7ada63 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -4901,6 +4901,11 @@ union mlx5_ifc_field_select_802_1_r_roce_auto_bits { u8 reserved_at_0[0x20]; }; =20 +struct mlx5_ifc_rs_histogram_cntrs_bits { + u8 hist[16][0x40]; + u8 reserved_at_400[0x2c0]; +}; + union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_= data_layout; struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_da= ta_layout; @@ -4915,6 +4920,7 @@ union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_= cntrs; struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs; + struct mlx5_ifc_rs_histogram_cntrs_bits rs_histogram_cntrs; u8 reserved_at_0[0x7c0]; }; =20 @@ -11738,6 +11744,28 @@ struct mlx5_ifc_mtctr_reg_bits { u8 second_clock_timestamp[0x40]; }; =20 +struct mlx5_ifc_bin_range_layout_bits { + u8 reserved_at_0[0xa]; + u8 high_val[0x6]; + u8 reserved_at_10[0xa]; + u8 low_val[0x6]; +}; + +struct mlx5_ifc_pphcr_reg_bits { + u8 active_hist_type[0x4]; + u8 reserved_at_4[0x4]; + u8 local_port[0x8]; + u8 reserved_at_10[0x10]; + + u8 reserved_at_20[0x8]; + u8 num_of_bins[0x8]; + u8 reserved_at_30[0x10]; + + u8 reserved_at_40[0x40]; + + struct mlx5_ifc_bin_range_layout_bits bin_range[16]; +}; + union mlx5_ifc_ports_control_registers_document_bits { struct mlx5_ifc_bufferx_reg_bits bufferx_reg; struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_da= ta_layout; @@ -11804,6 +11832,7 @@ union mlx5_ifc_ports_control_registers_document_bit= s { struct mlx5_ifc_mtmp_reg_bits mtmp_reg; struct mlx5_ifc_mtptm_reg_bits mtptm_reg; struct mlx5_ifc_mtctr_reg_bits mtctr_reg; + struct mlx5_ifc_pphcr_reg_bits pphcr_reg; u8 reserved_at_0[0x60e0]; }; =20 base-commit: 04a3134f88a4bd03001a3093144819523cfca99e --=20 2.31.1