From nobody Fri Oct 3 23:02:53 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36E5329BD8E; Fri, 22 Aug 2025 19:09:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755889774; cv=none; b=Yf4RvwspxakcTEvgDhYwxr46JYZxuMZ5MzJCTf04etlbElYCRvmCjylvS07nHO/Fw/4YMrP+wzOg/xhLVn/ut2LVmFswLDKh9/P93iwt6CKHOmmlUKz22S6lfh8kcPs7h0MiHddRmv+zdXAKl32U+IM4xUrael8g2+EJ9WgdMzk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755889774; c=relaxed/simple; bh=ovMpWUhaVgi2kYqaDIh/Glgpnpo4K6hFWXL6hr4gVhA=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=RHe25g0onF04DX6Ye6NaCDIhgXn+tJNB7mQd8tvAz5FQrNk8nE4/4duFWUIOslCf5weTvl07UR6NRcKd4Vzq+ioWQ/BfFtJ0F7YX34NydjQOvLZy8lxKJLlA7VS6iUApT787ZJM8YuvAyif5334lxKzznA+jjggvU+KOoJIx8ss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Kbx/Cq5u; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=AG/TqXVM; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Kbx/Cq5u"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="AG/TqXVM" Date: Fri, 22 Aug 2025 19:09:27 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755889769; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=P7LSD5wdloEL16KIrxIAb0rEmVcsCfb39HPPpvpLR8k=; b=Kbx/Cq5u6anKv2NSNgqkdjDTYF0JcaRsfQq23RImX2vR9+ldgeftQQcTFXZeUotrNMWm0W p2yvZvoFzy+w7kT1t37TguCo5xaJ9u5F22qvEt8TpvRTt3Y01JtwbGeAVw7V4rcBQ9K3RZ ce30Hmjl5Zt/m8iL6JrEQIDF9uH9MjdUtmolL4BPFD6qpj7quM7mqHVk7IeDeKCqcVv1rC M+4JEz5jaze8qu85+klZLdCKMqIwn+xB9/nJWvL+P+yzbkAnIIrvA4GpWnXYwglT4p2lBA FhNnzfPSfGvcJUKyM1Eht2qexfKnz4JKomISpgwWqYZf1DT7hOH/8XQPVOVOtw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755889769; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=P7LSD5wdloEL16KIrxIAb0rEmVcsCfb39HPPpvpLR8k=; b=AG/TqXVMENl6KPzM1LikaaeeTeDqcanHXBt0JTfZ9CwgybjaaEk+u92ZyG4DDhFUxzohni qE2JgthqY+KLhmAw== From: "tip-bot2 for Suchit Karunakaran" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] x86/cpu/intel: Fix the constant_tsc model check for Pentium 4 Cc: Suchit Karunakaran , Dave Hansen , Sohil Mehta , stable@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <175588976768.1420.16910015408694101752.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 1a77c102cee20edb2459334d8eaf3202697ac8f5 Gitweb: https://git.kernel.org/tip/1a77c102cee20edb2459334d8eaf32026= 97ac8f5 Author: Suchit Karunakaran AuthorDate: Sat, 16 Aug 2025 12:21:26 +05:30 Committer: Dave Hansen CommitterDate: Fri, 22 Aug 2025 12:02:59 -07:00 x86/cpu/intel: Fix the constant_tsc model check for Pentium 4 Pentium 4's which are INTEL_P4_PRESCOTT (model 0x03) and later have a constant TSC. This was correctly captured until commit fadb6f569b10 ("x86/cpu/intel: Limit the non-architectural constant_tsc model checks"). In that commit, an error was introduced while selecting the last P4 model (0x06) as the upper bound. Model 0x06 was transposed to INTEL_P4_WILLAMETTE, which is just plain wrong. That was presumably a simple typo, probably just copying and pasting the wrong P4 model. Fix the constant TSC logic to cover all later P4 models. End at INTEL_P4_CEDARMILL which accurately corresponds to the last P4 model. Fixes: fadb6f569b10 ("x86/cpu/intel: Limit the non-architectural constant_t= sc model checks") Signed-off-by: Suchit Karunakaran Signed-off-by: Dave Hansen Reviewed-by: Sohil Mehta Cc:stable@vger.kernel.org Link: https://lore.kernel.org/all/20250816065126.5000-1-suchitkarunakaran%4= 0gmail.com --- arch/x86/kernel/cpu/intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 076eaa4..98ae4c3 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -262,7 +262,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) if (c->x86_power & (1 << 8)) { set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); - } else if ((c->x86_vfm >=3D INTEL_P4_PRESCOTT && c->x86_vfm <=3D INTEL_P4= _WILLAMETTE) || + } else if ((c->x86_vfm >=3D INTEL_P4_PRESCOTT && c->x86_vfm <=3D INTEL_P4= _CEDARMILL) || (c->x86_vfm >=3D INTEL_CORE_YONAH && c->x86_vfm <=3D INTEL_IVYBRIDGE= )) { set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); }