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Wed, 13 Aug 2025 12:20:21 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Dragos Tatulea , Daniel Jurgens , William Tu Subject: [PATCH net-next 2/2] net/mlx5: Support disabling host PFs Date: Wed, 13 Aug 2025 22:19:56 +0300 Message-ID: <1755112796-467444-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1755112796-467444-1-git-send-email-tariqt@nvidia.com> References: <1755112796-467444-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE9:EE_|LV3PR12MB9233:EE_ X-MS-Office365-Filtering-Correlation-Id: 0554b0e2-58e0-4e06-d384-08ddda9e80f3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?tZ5YS5kR/dwmPnlYi40tyj5uLXspX62mFInEKl1G5p72ZF97XYk9C8Hb9v+1?= =?us-ascii?Q?HOqbd6XEgd6mU1MC//eSv1kBH/XHTLJvZS4ZCxDhH7gfhxPqoWx4t4bNuzqC?= =?us-ascii?Q?NdNn2SpFdp+66kK9wyugTfKQlRieckZIfO0H9ogrs1bhWZM8RarA3SY6e4L9?= =?us-ascii?Q?6gu+sQcVGTl/EYqMzIYHi9/v0kzrYjIpCBMV086CohwmbssCiEZAURqqGwWh?= =?us-ascii?Q?q/jqS4JCc3Zualc/lSqI+zdzyL12ph5YFs/spN0heI558fZ92Cr1YHiDijld?= =?us-ascii?Q?XwEFI9vUFEfpmBmUqhFRxHGuT/1ue11l8kcg4gtGl1E/vS6/5OVDoJxXetK4?= =?us-ascii?Q?nqWZ+eDtSxT2PNP69beNPApc/pmWTUJvswUDDK+EISRNtGz/Cef52ff9kSa/?= =?us-ascii?Q?Nyh38dhShssTDRchMG1C8RN0GP8TyqmGeqDLMYnWsr5Xe7SztnLtHI0dJF6M?= =?us-ascii?Q?IH4DMj/cs4qdMIdvtZV3fqdpsAhR1TfqdXdNC4G8CiuNriQXFJ4virEu3PJT?= =?us-ascii?Q?Lbm8p1o2m1Yhcejl+6uEAZ0locUmv5+Ak7R33yRRthVRFuwh6GOeAxwxOEC8?= =?us-ascii?Q?vFt0nFCJvRtc2d/chNGpC2dxG4FGodfvlXAirMcTs8wSpDHe2abTKmeapZWT?= =?us-ascii?Q?O0LSrJQfnkva/5ZyHn4BZQgCFbOwrrVFbDuZFfv2gyJSsDV+5pM3KCRK1AUw?= =?us-ascii?Q?igD9RiCNF2hsjh+T7OlaY3g5rqm7ofmqzNv3kKfelzCquaofq41B1s916l1L?= =?us-ascii?Q?xcJx3bVIrjpOS7EOtzQbkZsmUp2R3EguAasw7BFILczqWUGJMQfswFMFivHk?= =?us-ascii?Q?XFMFGD31korSZOwN449KG+cmMeQn9N96IKQnBqjLf3ti7LVmyfBAnWLG6w5n?= =?us-ascii?Q?k95ytk+WXINKimtDjwNn5ULZ3xdzSn2jtQ7fypkTWsYh6OIbMJLSWGxnheze?= =?us-ascii?Q?Gcw8IWVvtbIQ77gv3QH49wXhkwp4poLkGTZz+TUTLaCirQlQvvMC9nk6egQ1?= =?us-ascii?Q?Pma2e0qnbmXORrrGRiU2d7MzTyil2pThNUNYP9nQ5ONKzl1B49VowekXqsxv?= =?us-ascii?Q?juRs6I3ndSGs8w2qO7wEEnTaaRaJFz/n9l8tYStRfj9kn15d20u87vGO+bdB?= =?us-ascii?Q?bRb/5Tr2oCddzyJb2YZ17f4m7Prm4NbMS/f1XqeletjZleL3ONcjdbMVzfNb?= =?us-ascii?Q?7rqlUwbF34i8G0YwOlVCANT6YCaQXhal4PlDXsxYNRNugTGShFDgxA5kIQJ2?= =?us-ascii?Q?mYJehh7TDXnSXZLPrADOy73meyex3MXdEc7PYgJkY4y8z5je6rxsZtpFsSjR?= =?us-ascii?Q?uMqo86orXOOP83P81pPAlExd71sIu8AUYssz5nNBbge9NTKX3zY4q++V9qSe?= =?us-ascii?Q?r6MVwv0E65n5PECzz5oTtFK0qEujPdzdRjpAzJ30cCEaKLIhN+jFnbSwu45F?= =?us-ascii?Q?4DJounwCc+J0pJiUDU+iuqNPdy+R7EOx8xwAr3Rx60QwpMlcPxPblD4bR6mk?= =?us-ascii?Q?YX6+GMda6VuUbeF5qQ9qP0r58Tm8sqGXT3Cl?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 19:20:45.8263 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0554b0e2-58e0-4e06-d384-08ddda9e80f3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9233 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Daniel Jurgens Some devices support disabling the physical function on the host. When this is configured the vports for the host functions do not exist. This patch checks if host functions are enabled before trying to access their vports. Signed-off-by: Daniel Jurgens Reviewed-by: William Tu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 62 ++++++++++++------- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 7 +++ .../mellanox/mlx5/core/eswitch_offloads.c | 34 +++++----- 3 files changed, 66 insertions(+), 37 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 31059fff30ec..3d533061311b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1297,17 +1297,19 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitc= h *esw, esw->mode =3D=3D MLX5_ESWITCH_LEGACY; =20 /* Enable PF vport */ - if (pf_needed) { + if (pf_needed && mlx5_esw_host_functions_enabled(esw->dev)) { ret =3D mlx5_eswitch_load_pf_vf_vport(esw, MLX5_VPORT_PF, enabled_events); if (ret) return ret; } =20 - /* Enable external host PF HCA */ - ret =3D host_pf_enable_hca(esw->dev); - if (ret) - goto pf_hca_err; + if (mlx5_esw_host_functions_enabled(esw->dev)) { + /* Enable external host PF HCA */ + ret =3D host_pf_enable_hca(esw->dev); + if (ret) + goto pf_hca_err; + } =20 /* Enable ECPF vport */ if (mlx5_ecpf_vport_exists(esw->dev)) { @@ -1339,9 +1341,10 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch= *esw, if (mlx5_ecpf_vport_exists(esw->dev)) mlx5_eswitch_unload_pf_vf_vport(esw, MLX5_VPORT_ECPF); ecpf_err: - host_pf_disable_hca(esw->dev); + if (mlx5_esw_host_functions_enabled(esw->dev)) + host_pf_disable_hca(esw->dev); pf_hca_err: - if (pf_needed) + if (pf_needed && mlx5_esw_host_functions_enabled(esw->dev)) mlx5_eswitch_unload_pf_vf_vport(esw, MLX5_VPORT_PF); return ret; } @@ -1361,10 +1364,12 @@ void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_= eswitch *esw) mlx5_eswitch_unload_pf_vf_vport(esw, MLX5_VPORT_ECPF); } =20 - host_pf_disable_hca(esw->dev); + if (mlx5_esw_host_functions_enabled(esw->dev)) + host_pf_disable_hca(esw->dev); =20 - if (mlx5_core_is_ecpf_esw_manager(esw->dev) || - esw->mode =3D=3D MLX5_ESWITCH_LEGACY) + if ((mlx5_core_is_ecpf_esw_manager(esw->dev) || + esw->mode =3D=3D MLX5_ESWITCH_LEGACY) && + mlx5_esw_host_functions_enabled(esw->dev)) mlx5_eswitch_unload_pf_vf_vport(esw, MLX5_VPORT_PF); } =20 @@ -1693,7 +1698,8 @@ int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_de= v *dev, u16 *max_sfs, u16 * void *hca_caps; int err; =20 - if (!mlx5_core_is_ecpf(dev)) { + if (!mlx5_core_is_ecpf(dev) || + !mlx5_esw_host_functions_enabled(dev)) { *max_sfs =3D 0; return 0; } @@ -1769,21 +1775,23 @@ static int mlx5_esw_vports_init(struct mlx5_eswitch= *esw) =20 xa_init(&esw->vports); =20 - err =3D mlx5_esw_vport_alloc(esw, idx, MLX5_VPORT_PF); - if (err) - goto err; - if (esw->first_host_vport =3D=3D MLX5_VPORT_PF) - xa_set_mark(&esw->vports, idx, MLX5_ESW_VPT_HOST_FN); - idx++; - - for (i =3D 0; i < mlx5_core_max_vfs(dev); i++) { - err =3D mlx5_esw_vport_alloc(esw, idx, idx); + if (mlx5_esw_host_functions_enabled(dev)) { + err =3D mlx5_esw_vport_alloc(esw, idx, MLX5_VPORT_PF); if (err) goto err; - xa_set_mark(&esw->vports, idx, MLX5_ESW_VPT_VF); - xa_set_mark(&esw->vports, idx, MLX5_ESW_VPT_HOST_FN); + if (esw->first_host_vport =3D=3D MLX5_VPORT_PF) + xa_set_mark(&esw->vports, idx, MLX5_ESW_VPT_HOST_FN); idx++; + for (i =3D 0; i < mlx5_core_max_vfs(dev); i++) { + err =3D mlx5_esw_vport_alloc(esw, idx, idx); + if (err) + goto err; + xa_set_mark(&esw->vports, idx, MLX5_ESW_VPT_VF); + xa_set_mark(&esw->vports, idx, MLX5_ESW_VPT_HOST_FN); + idx++; + } } + base_sf_num =3D mlx5_sf_start_function_id(dev); for (i =3D 0; i < mlx5_sf_max_functions(dev); i++) { err =3D mlx5_esw_vport_alloc(esw, idx, base_sf_num + i); @@ -1883,6 +1891,7 @@ int mlx5_eswitch_init(struct mlx5_core_dev *dev) goto free_esw; =20 esw->dev =3D dev; + dev->priv.eswitch =3D esw; esw->manager_vport =3D mlx5_eswitch_manager_vport(dev); esw->first_host_vport =3D mlx5_eswitch_first_host_vport_num(dev); =20 @@ -1901,7 +1910,6 @@ int mlx5_eswitch_init(struct mlx5_core_dev *dev) if (err) goto abort; =20 - dev->priv.eswitch =3D esw; err =3D esw_offloads_init(esw); if (err) goto reps_err; @@ -2433,3 +2441,11 @@ void mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev= *dev) dev->num_ipsec_offloads--; mutex_unlock(&esw->state_lock); } + +bool mlx5_esw_host_functions_enabled(const struct mlx5_core_dev *dev) +{ + if (!dev->priv.eswitch) + return true; + + return !dev->priv.eswitch->esw_funcs.host_funcs_disabled; +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 6d86db20f468..6c72080ac2a1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -899,6 +899,7 @@ int mlx5_esw_ipsec_vf_packet_offload_set(struct mlx5_es= witch *esw, struct mlx5_v bool enable); int mlx5_esw_ipsec_vf_packet_offload_supported(struct mlx5_core_dev *dev, u16 vport_num); +bool mlx5_esw_host_functions_enabled(const struct mlx5_core_dev *dev); #else /* CONFIG_MLX5_ESWITCH */ /* eswitch API stubs */ static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0= ; } @@ -966,6 +967,12 @@ static inline bool mlx5_eswitch_block_ipsec(struct mlx= 5_core_dev *dev) } =20 static inline void mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev *dev) {} + +static inline bool +mlx5_esw_host_functions_enabled(const struct mlx5_core_dev *dev) +{ + return true; +} #endif /* CONFIG_MLX5_ESWITCH */ =20 #endif /* __MLX5_ESWITCH_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index bee906661282..8ec9c0e0f4b9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -1213,7 +1213,8 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_es= witch *esw, misc =3D MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); =20 - if (mlx5_core_is_ecpf_esw_manager(peer_dev)) { + if (mlx5_core_is_ecpf_esw_manager(peer_dev) && + mlx5_esw_host_functions_enabled(peer_dev)) { peer_vport =3D mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF); esw_set_peer_miss_rule_source_port(esw, peer_esw, spec, MLX5_VPORT_PF); @@ -1239,19 +1240,21 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_= eswitch *esw, flows[peer_vport->index] =3D flow; } =20 - mlx5_esw_for_each_vf_vport(peer_esw, i, peer_vport, - mlx5_core_max_vfs(peer_dev)) { - esw_set_peer_miss_rule_source_port(esw, - peer_esw, - spec, peer_vport->vport); + if (mlx5_esw_host_functions_enabled(esw->dev)) { + mlx5_esw_for_each_vf_vport(peer_esw, i, peer_vport, + mlx5_core_max_vfs(peer_dev)) { + esw_set_peer_miss_rule_source_port(esw, peer_esw, + spec, + peer_vport->vport); =20 - flow =3D mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw), - spec, &flow_act, &dest, 1); - if (IS_ERR(flow)) { - err =3D PTR_ERR(flow); - goto add_vf_flow_err; + flow =3D mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw), + spec, &flow_act, &dest, 1); + if (IS_ERR(flow)) { + err =3D PTR_ERR(flow); + goto add_vf_flow_err; + } + flows[peer_vport->index] =3D flow; } - flows[peer_vport->index] =3D flow; } =20 if (mlx5_core_ec_sriov_enabled(peer_dev)) { @@ -1301,7 +1304,9 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_es= witch *esw, mlx5_del_flow_rules(flows[peer_vport->index]); } add_ecpf_flow_err: - if (mlx5_core_is_ecpf_esw_manager(peer_dev)) { + + if (mlx5_core_is_ecpf_esw_manager(peer_dev) && + mlx5_esw_host_functions_enabled(peer_dev)) { peer_vport =3D mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF); mlx5_del_flow_rules(flows[peer_vport->index]); } @@ -4059,7 +4064,8 @@ mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch = *esw, u16 vport_num) { /* Currently, only ECPF based device has representor for host PF. */ if (vport_num =3D=3D MLX5_VPORT_PF && - !mlx5_core_is_ecpf_esw_manager(esw->dev)) + (!mlx5_core_is_ecpf_esw_manager(esw->dev) || + !mlx5_esw_host_functions_enabled(esw->dev))) return false; =20 if (vport_num =3D=3D MLX5_VPORT_ECPF && --=20 2.31.1