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Tue, 12 Aug 2025 07:18:11 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Gal Pressman , Thomas Gleixner , Carolina Jubran , Vladimir Oltean , "Dragos Tatulea" Subject: [PATCH net-next V2 3/3] net/mlx5: Support getcyclesx and getcrosscycles Date: Tue, 12 Aug 2025 17:17:08 +0300 Message-ID: <1755008228-88881-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1755008228-88881-1-git-send-email-tariqt@nvidia.com> References: <1755008228-88881-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D9:EE_|DM4PR12MB6421:EE_ X-MS-Office365-Filtering-Correlation-Id: f0652e7e-e2be-457d-32c7-08ddd9ab1c7e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?SWpCbXJwWmFNMEFDN0J5dExyajAxN3plS1NSdlZTU1l6UXJUY0d5b3krSzEv?= =?utf-8?B?cTU5THVHYTRFTFB0eURqQ1Z0THRVSkllMEdybUhMamU5aHIxRmJJTE5XbGVz?= =?utf-8?B?WG16Sm5ZWVNScDhGMkhBREhKaUVLNlRORjh5RzA0bktSQWluQjNLSFdITk1q?= =?utf-8?B?VTdjTzdtdTd4STdmbnZKS0JqSnFkOE11VEdWMGVqSExDek1KWEpuZTJkV0NR?= =?utf-8?B?SG9TOWlVTjlmcmpWdlNzTnZOU3NscGdRRk11Uks3eE5tcktnOHVMeXY2WTNC?= =?utf-8?B?WFNHODE5bERvdzhUNWM1dDM5VDJGbG54VldHNWdydHdnaDV4MnJta2s3VDky?= =?utf-8?B?a3JyeWZiMzQ0OW80NG5NUnd5OFowN3lZQ1ZuRkxTcjcxc1RkTW5nc1FMVjJC?= =?utf-8?B?MXNzU2M2TXZYTzdvRnlNVDAwSzhidDJkVUhXVWZ5bjZlQ3hUYmN5ckdGdDVR?= =?utf-8?B?N0RRV1NWRmxZRkY0Ri9SVDFMWDl0NlgzTXZ4OGJoUGswb2VlS01ZeHRGcXkz?= =?utf-8?B?NUZ6Q1FCK2JHdHpBUEM5VkpLNG92d1FXU1E3R0Q5ME8zekRVSXpZakZYSEYv?= =?utf-8?B?dURSdVBLOUZ6SzNVOThES1JBd1FDdk95UGR4Um1mR0RwVkV3VlB0V3lwdm51?= =?utf-8?B?TG01c2hYQmM2S1pqY3VLdUlVaU95R3ZGazEyR3k5Uks0MDBrUStZTkZqVU1x?= =?utf-8?B?ZktLTS9DQnJRMEhHZ2ZYTHBKVnRFYXFIbWlJT0dWUGt4UWxHMFZubnpjSzZs?= =?utf-8?B?OE9xZGhRdTNqMUVJZDAyTjQ0VDNlMy91OHN0blJpTzBZTkNKUUk3MnlLRWVl?= =?utf-8?B?VnJqVjlhSFNJVVdSM29jRzUwNmtlR0ZYeHVFNXdkT3hDUGVnUWd1R2hXeTI2?= =?utf-8?B?MWVRUVNkTDJETWpydmJpZWErd0hpVEpWUjVOaWEvaUExclJqaHUxMDlOVTV5?= =?utf-8?B?dWUzc2d6V3dkdzhIdjNneGw3ZUhLYytzV1Q2WXNDT1FNSm0rL29jdUZjOTRQ?= =?utf-8?B?aG41ZFRadHVudVNDL3VudzQ5NXlKYkc0SHVPN1htd2o0UjZMRDdIQWlQVDAr?= =?utf-8?B?b1NlbTVRUjBpTElKTkhBcmhvS1QzckFXQlVLYmt5VGNSTTBkek12L215N1Fz?= =?utf-8?B?eGRIYnh1cHZRejN4M0I2TXZxZ3hHQU5hSjl1UlQvMWlxT1J1aHlGT2tKNm1x?= =?utf-8?B?T0NhOUJ1MTRWMU1DNjNXM3EyV2Y1T2NxdDNoT0c4S1NybFVhdDBvajB3Ukto?= =?utf-8?B?TlJXWGFlUkt0ckZUdGxJMUFWbyttc2o4am82c0xQcjBiWm5hRDhxQkFRdlNK?= =?utf-8?B?T3JoWXpHb0lvelgyZk9RR1lDcEhHV0h0dkprZ2xOVEoraGloZjY5QkJJRlJ3?= =?utf-8?B?dm9OWEgxaEpXUFFjdjhDZWM2amxzSWxNYmtYNkVnS1BSWDM1SUVGMXpCRzFm?= =?utf-8?B?VjU3TVhIbkpkeXYyYjVIeFBXWGRuVnlzRTBPRXdiZk5kRVRaa3Z0SVlOenVJ?= =?utf-8?B?MVpRU2ZxbG5kM2NiUkhIZTlCNFBDODVQYmhpZlptVnlJbytyckVhbUUxcGI4?= =?utf-8?B?dExPUkk3Y3dkTVJycEtVWVowcGZlWWtndnNBQkV6VXQ0QWFDbThGWVJhQTVG?= =?utf-8?B?NklvMTQ1YmVpVzdYdGp5cU9LZEFrUjZ5UzFnTjh3L01XQ2YrSVJoc1ljaWRm?= =?utf-8?B?dm0xVWdQTjR2bHRPSC82Y2tUdEcycjZLRGE4cVEvNGRZSGxFQ09MZjZxeUhq?= =?utf-8?B?bkI5VGZUU3RJZTJJcWVxYWlRVzZ6Q1hmWm9SV3ZxZkY4NnVCZytYWTlUN3pK?= =?utf-8?B?RUpRTEM1TnQ5c2p1eWhvTFQ3TjY0L09hTU1GVWhRZ25pZVh2VHRTUU5mbXJV?= =?utf-8?B?NjZyUmI5RnJSaUJDNzFZTW9IT0szYjRSemtJVlpmbkREZFEydGY0UXluamxV?= =?utf-8?B?ZlZXMXFzeEZ6cWxxRVdoN25CRUZ4a3NiUXltSmJVbWlJTHJGZ3NSSzFrdldL?= =?utf-8?B?bmNYbHFISktTUW9SSjdIY09laUwwYjhvSnZuTHFKeGVSVnU1dE01amJwWmZi?= =?utf-8?Q?Qzxt2Q?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2025 14:18:29.6400 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f0652e7e-e2be-457d-32c7-08ddd9ab1c7e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D9.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6421 From: Carolina Jubran Implement the getcyclesx64 and getcrosscycles callbacks in ptp_info to expose the device=E2=80=99s raw free-running counter. Signed-off-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 74 ++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/= net/ethernet/mellanox/mlx5/core/lib/clock.c index 9b49bdc339ad..7ad3baca99de 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -306,6 +306,23 @@ static int mlx5_mtctr_syncdevicetime(ktime_t *device_t= ime, return 0; } =20 +static int +mlx5_mtctr_syncdevicecyclestime(ktime_t *device_time, + struct system_counterval_t *sys_counterval, + void *ctx) +{ + struct mlx5_core_dev *mdev =3D ctx; + u64 device; + int err; + + err =3D mlx5_mtctr_read(mdev, false, sys_counterval, &device); + if (err) + return err; + *device_time =3D ns_to_ktime(device); + + return 0; +} + static int mlx5_ptp_getcrosststamp(struct ptp_clock_info *ptp, struct system_device_crosststamp *cts) { @@ -330,6 +347,32 @@ static int mlx5_ptp_getcrosststamp(struct ptp_clock_in= fo *ptp, mlx5_clock_unlock(clock); return err; } + +static int mlx5_ptp_getcrosscycles(struct ptp_clock_info *ptp, + struct system_device_crosststamp *cts) +{ + struct mlx5_clock *clock =3D + container_of(ptp, struct mlx5_clock, ptp_info); + struct system_time_snapshot history_begin =3D {0}; + struct mlx5_core_dev *mdev; + int err; + + mlx5_clock_lock(clock); + mdev =3D mlx5_clock_mdev_get(clock); + + if (!mlx5_is_ptm_source_time_available(mdev)) { + err =3D -EBUSY; + goto unlock; + } + + ktime_get_snapshot(&history_begin); + + err =3D get_device_system_crosststamp(mlx5_mtctr_syncdevicecyclestime, + mdev, &history_begin, cts); +unlock: + mlx5_clock_unlock(clock); + return err; +} #endif /* CONFIG_X86 */ =20 static u64 mlx5_read_time(struct mlx5_core_dev *dev, @@ -528,6 +571,24 @@ static int mlx5_ptp_gettimex(struct ptp_clock_info *pt= p, struct timespec64 *ts, return 0; } =20 +static int mlx5_ptp_getcyclesx(struct ptp_clock_info *ptp, + struct timespec64 *ts, + struct ptp_system_timestamp *sts) +{ + struct mlx5_clock *clock =3D container_of(ptp, struct mlx5_clock, + ptp_info); + struct mlx5_core_dev *mdev; + u64 cycles; + + mlx5_clock_lock(clock); + mdev =3D mlx5_clock_mdev_get(clock); + + cycles =3D mlx5_read_time(mdev, sts, false); + *ts =3D ns_to_timespec64(cycles); + mlx5_clock_unlock(clock); + return 0; +} + static int mlx5_ptp_adjtime_real_time(struct mlx5_core_dev *mdev, s64 delt= a) { u32 in[MLX5_ST_SZ_DW(mtutc_reg)] =3D {}; @@ -1244,6 +1305,7 @@ static void mlx5_init_timer_max_freq_adjustment(struc= t mlx5_core_dev *mdev) static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) { struct mlx5_clock *clock =3D mdev->clock; + bool expose_cycles; =20 /* Configure the PHC */ clock->ptp_info =3D mlx5_ptp_clock_info; @@ -1251,12 +1313,22 @@ static void mlx5_init_timer_clock(struct mlx5_core_= dev *mdev) if (MLX5_CAP_MCAM_REG(mdev, mtutc)) mlx5_init_timer_max_freq_adjustment(mdev); =20 + expose_cycles =3D !MLX5_CAP_GEN(mdev, disciplined_fr_counter) || + !mlx5_real_time_mode(mdev); + #ifdef CONFIG_X86 if (MLX5_CAP_MCAM_REG3(mdev, mtptm) && - MLX5_CAP_MCAM_REG3(mdev, mtctr) && boot_cpu_has(X86_FEATURE_ART)) + MLX5_CAP_MCAM_REG3(mdev, mtctr) && boot_cpu_has(X86_FEATURE_ART)) { clock->ptp_info.getcrosststamp =3D mlx5_ptp_getcrosststamp; + if (expose_cycles) + clock->ptp_info.getcrosscycles =3D + mlx5_ptp_getcrosscycles; + } #endif /* CONFIG_X86 */ =20 + if (expose_cycles) + clock->ptp_info.getcyclesx64 =3D mlx5_ptp_getcyclesx; + mlx5_timecounter_init(mdev); mlx5_init_clock_info(mdev); mlx5_init_overflow_period(mdev); --=20 2.40.1