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Thu, 17 Jul 2025 10:04:23 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Saeed Mahameed , "Tariq Toukan" , Mark Bloch , , , , Alexandre Cassen , "Leon Romanovsky" Subject: [PATCH net-next 1/3] net/mlx5e: Support routed networks during IPsec MACs initialization Date: Thu, 17 Jul 2025 20:03:10 +0300 Message-ID: <1752771792-265762-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752771792-265762-1-git-send-email-tariqt@nvidia.com> References: <1752771792-265762-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB74:EE_|CH3PR12MB8936:EE_ X-MS-Office365-Filtering-Correlation-Id: 05b7b557-c1d7-44ec-4516-08ddc5540941 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026|15866825006|41080700001; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?swYRFNWTQQz0wJKT8zcCi2tNPal+e2rTlUXyO7zD5FotQl8pjkTEbzkoosOZ?= =?us-ascii?Q?dfcgMz6qFFLb3Dg7In7c5u1Cm2npCE0JbZcB3IzpDA4pQsvcP+q6+0kIQi/v?= =?us-ascii?Q?w1IGDNeCNBxwFHiNJsaNUKrJEGlrQxE6kH8IvDfS2vcPxyidGE+1Em922PJg?= =?us-ascii?Q?YrE1lrmCuc6k7ZlO+61P2KFVzk+Vxah2dDlD9Q3pR5PJN0xkNgfTDyvZBMpr?= =?us-ascii?Q?If6jDtLBmnquQ11LtaYf1SYDykSFpAZxgbZOUiMfIrtBDY93jVLHm8yJngZ4?= =?us-ascii?Q?MUL2JmXIYyEci10cMI6sZvaAd1hM8GfZBO7tI4cwmYlAifDnEE9Dpn2GAi7/?= =?us-ascii?Q?JevBQjW9KKh/rNMUtvRf/8s0gc9QgoA9kagFSHI7sVQQ2pAImUjYEFdLH3g2?= =?us-ascii?Q?2/n3veu75UWDO3u1zxFGBzxvjGsWEj8myg0CDWbFFBLBIBg4D3qN4K8BD3Av?= =?us-ascii?Q?UVbwF1IQsxthN4kLkiBweD51kFS4iUPL9v1lj888AlM6QMhrzGonI9ZA5Qyr?= =?us-ascii?Q?g1+UDQ66bP573GJTHXkC4HjtPNd8fovtqraicwkvgIRXHlJArMkpYK5D1znb?= =?us-ascii?Q?zzY0Q+s2YlcCABQDFFUf1gabdfvC4REiSFxNbub8vz2Hy7CTYehrUG6kwOiO?= =?us-ascii?Q?8KcGNfF9Z2QBMRgVA3AjtuATVvKfzMgAemMXt1nH65I7Q8EAPAS8b8CiDQXK?= =?us-ascii?Q?6GErV/Dffyjtklw6rvVTwjhyP2ODRYqg3YdNbGvM5JRFQb+VjCBKjVWbOrnb?= =?us-ascii?Q?oDcAIVfKNcOFzssnh7XyroRaFoBZ5ScwiWc8LNUIzb6Vb1BNqhnzDJhbtRmp?= =?us-ascii?Q?DeC5ClwF7LYf+SvDCRiI5ZxFvVIQx5qd3bngJkmyYSXQU6waO2gGGkDwQAgp?= =?us-ascii?Q?P1g5lYU6U5q11eo2lNdz8Uc+r6UrzcnkS/jjdgEVb1DkVPYi+eFEklSriXQt?= =?us-ascii?Q?bvfFNvMN7FoOoSXI+3RsCqijZtH4yQYJIyjFyBMLHp/i+tHQ6MUdZJsHg+S/?= =?us-ascii?Q?lB3iimiqDms6WGFk1+12Rba4BZYF9Fpss3Gf/xCS7ZXg5un32OJjlbHKDJTu?= =?us-ascii?Q?5ICqi7qgdHbQJxXgxwnO44FedmH08upJc2avsJsDsf6IiumjNCMsmYVd6mKW?= =?us-ascii?Q?kus61oHU0Ph07GLAXbHsNKSjkv+p6HwiaidKMFYz/MMF5tF8q8QAnJfww5+E?= =?us-ascii?Q?JEd68VLkL0PAxi9LCGWAThbYgwOAnCN957+p0p2x1ao9qVBpnNU5bKJU4/jk?= =?us-ascii?Q?3e85IcEWfSRsFqsqVJkxDfdMNsSoX4F0gKQmlb+3ySGbv+pRa9/HNqaBsh+k?= =?us-ascii?Q?vsV2PyJKftrMGeVXEqNRENfogzby8p4gluWQJ/eIPvFaP2XJMR3yCy+lJGbe?= =?us-ascii?Q?5mpnItZJQmKLj38a7S6sPs5qKH1ixQG0xKLisPbblJyOlcs5kKkxboCKKrXT?= =?us-ascii?Q?omXZ3snDXvm4PK+WRhEM/G2UhNzHkaRwzGYyLTU3zE8qU6pNzJPsuxB7WEhO?= =?us-ascii?Q?VAteu9OzZMDZ8yeRCksb57I/pbK+pDPLOEj2UZPHnUJOEJnM4wBTT1QopPU0?= =?us-ascii?Q?IMaXndXhSaMuIUy/jPZJzJqcekXFk3KgEu3ARU/k?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026)(15866825006)(41080700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2025 17:04:47.7831 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05b7b557-c1d7-44ec-4516-08ddc5540941 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8936 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Alexandre Cassen Remote IPsec tunnel endpoint may refer to a network segment that is not directly connected to the host. In such a case, IPsec tunnel endpoints are connected to a router and reachable via a routing path. In IPsec packet offload mode, HW is initialized with the MAC address of both IPsec tunnel endpoints. Extend the current IPsec init MACs procedure to resolve nexthop for routed networks. Direct neighbour lookup and probe is still used for directly connected networks and as a fallback mechanism if fib lookup fails. Signed-off-by: Alexandre Cassen Signed-off-by: Leon Romanovsky Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/ipsec.c | 82 ++++++++++++++++++- 1 file changed, 80 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/dri= vers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index 77f61cd28a79..a486684c8e60 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -36,6 +36,7 @@ #include #include #include +#include =20 #include "en.h" #include "eswitch.h" @@ -260,8 +261,14 @@ static void mlx5e_ipsec_init_macs(struct mlx5e_ipsec_s= a_entry *sa_entry, { struct mlx5_core_dev *mdev =3D mlx5e_ipsec_sa2dev(sa_entry); struct net_device *netdev =3D sa_entry->dev; + struct mlx5e_ipsec_addr *addrs =3D &attrs->addrs; + struct xfrm_state *x =3D sa_entry->x; + struct dst_entry *rt_dst_entry; + struct flowi4 fl4 =3D {}; + struct flowi6 fl6 =3D {}; struct neighbour *n; u8 addr[ETH_ALEN]; + struct rtable *rt; const void *pkey; u8 *dst, *src; =20 @@ -274,18 +281,89 @@ static void mlx5e_ipsec_init_macs(struct mlx5e_ipsec_= sa_entry *sa_entry, case XFRM_DEV_OFFLOAD_IN: src =3D attrs->dmac; dst =3D attrs->smac; - pkey =3D &attrs->addrs.saddr.a4; + + switch (addrs->family) { + case AF_INET: + fl4.flowi4_proto =3D x->sel.proto; + fl4.daddr =3D addrs->saddr.a4; + fl4.saddr =3D addrs->daddr.a4; + pkey =3D &addrs->saddr.a4; + break; + case AF_INET6: + fl6.flowi6_proto =3D x->sel.proto; + memcpy(fl6.daddr.s6_addr32, addrs->saddr.a6, 16); + memcpy(fl6.saddr.s6_addr32, addrs->daddr.a6, 16); + pkey =3D &addrs->saddr.a6; + break; + default: + return; + } break; case XFRM_DEV_OFFLOAD_OUT: src =3D attrs->smac; dst =3D attrs->dmac; - pkey =3D &attrs->addrs.daddr.a4; + switch (addrs->family) { + case AF_INET: + fl4.flowi4_proto =3D x->sel.proto; + fl4.daddr =3D addrs->daddr.a4; + fl4.saddr =3D addrs->saddr.a4; + pkey =3D &addrs->daddr.a4; + break; + case AF_INET6: + fl6.flowi6_proto =3D x->sel.proto; + memcpy(fl6.daddr.s6_addr32, addrs->daddr.a6, 16); + memcpy(fl6.saddr.s6_addr32, addrs->saddr.a6, 16); + pkey =3D &addrs->daddr.a6; + break; + default: + return; + } break; default: return; } =20 ether_addr_copy(src, addr); + + /* Destination can refer to a routed network, so perform FIB lookup + * to resolve nexthop and get its MAC. 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Miller" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Saeed Mahameed , "Tariq Toukan" , Mark Bloch , , , , Shay Drory Subject: [PATCH net-next 2/3] net/mlx5: Allocate cpu_mask on heap to fix frame size warning for large NR_CPUS Date: Thu, 17 Jul 2025 20:03:11 +0300 Message-ID: <1752771792-265762-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752771792-265762-1-git-send-email-tariqt@nvidia.com> References: <1752771792-265762-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB74:EE_|SA3PR12MB9107:EE_ X-MS-Office365-Filtering-Correlation-Id: 37b0a036-9914-4b32-b722-08ddc5540b00 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?b3h3cUcwRnJOYXhsY3BvdVhaVVVBRWEzMTBrdW8yNnAvOTZkcE11SStnZC80?= =?utf-8?B?QnFxTHdVYlgyclA3MjhCN09Pa2N3R0JOYVovbU5uRGYyVkllRzM4djE3N3hl?= =?utf-8?B?Q1lIRHF5Ylk2QkRnOTJyUFNPb3Z2bzk3M1M1eXZscXFINGhIa1NRM0ZBU0Mx?= =?utf-8?B?bWNRM3NzeUJQM0JZeUcrOE00OGVSTzRoc1VIYjlDalUyUzVvOWhKdXRhb0tV?= =?utf-8?B?VXdNUms3aGVEMDk3WU53dVBhUGFNQTdoRHFhZmNPUjIyQVJpTjlEc1FTTldl?= =?utf-8?B?TWlkSHpacjdUcGQ2NFlzWXAzdEZLd3c5RWplSGVFS1gvZXVQS1FmQnFtMjlQ?= =?utf-8?B?aFBQc2Y1NUlLZklzUHhYekNxa3ZIT2REQnRwVkdsMTFQckt2NUxMSVduN1Bh?= =?utf-8?B?U1FjOUJ3MU91b0F3UWZPdWxwTUJZQ1Y5WjlLTmFFWUZ6S1hQdHNFUExlZVhY?= =?utf-8?B?QTZoYVN5VFkzSHRPeWJBa3ZZM0JRMU9vWXl3Tk5qdG5nQXMxeDVKQ3NKbXNn?= =?utf-8?B?ZisxdEZLQkFqaGtoTGZSZGx1RnFaYWRWL0tHN0VpcWhKb21EZlh0aWFYcm5K?= =?utf-8?B?NDRUVFpETjVvNURSWE11MVQ0OWdwNXAwbkhRb1ZGWlBRbHlpcVBTZVg2NXBr?= =?utf-8?B?WHhVdWgxb01nZXVRMExtVmp5c2drT3k3ZEhVRzdCOW9lWWloRXRjV3FhVDF5?= =?utf-8?B?Sy9TTHY5cUhxZ3E4T05PWGVnS3VJWGYyNWhuRzRqN25HRFZqQXR0TkVaVnBv?= =?utf-8?B?R3ZuNWJlZ0dXYk9VdlNSeUJyaWR5ZlVWMHJtdFdZWnlEOUlGMkYvK3p1Zy9S?= =?utf-8?B?eVpRN1VtT1JkdWJmREh0ZC8zeEN5R1A2TlBNY0x4ek4wWmV0TzJsVmpraEMx?= =?utf-8?B?MHJFOUp4Ylc2TWN4LzcwZzZ1dnVDak1PMkJSQzd4QzhFM1pGYWlEckk5bE5N?= =?utf-8?B?UHFpMXVqMURwQktROE96S2tQaTVKdHNUSmlLajRyWGdZc1VQZE8rNlkrdVdQ?= =?utf-8?B?VThqL0VWN0laRjRZczZ5YTgzaXowbTlBUEZkcG1SRDBqV2xjanlhaW0wUEVU?= =?utf-8?B?OFVoUUVhSEFBcGFKL01QZG1RZE5tdTE3T3hjRlN2bWI5RXFKakpwckN6QVRu?= =?utf-8?B?ZTJNVC9abFVyUFpLaE9OMmVlUTRzYTFySytRN3hxWTE3ZjREcjRRWHJKQ0o3?= =?utf-8?B?YmNrUjhyYTk4dEJUbFlOay85MFQra1AzNWttRUtRRFd5LzVhL2hTU2pIYXdX?= =?utf-8?B?dFVvMWNuOUhjM2tRRXdhVEhteitBTVVaQW1wZFY3VHFrR2NrdUJxU1hGdjRG?= =?utf-8?B?dVNHaFRtSGx5MkJvQ21peWJCL3dtbEV0dTY3VC9WdVlpSk1SeVhNcTdmK0Ft?= =?utf-8?B?WGRGZENhdTRhdjR4V3FuYThBdll5djRLbWc5d3dEMk9VaEcrUnB0aUR0T2Fr?= =?utf-8?B?MzZzVGdoczZTSGV0VUwyREdyM1lGSXU3cFc5cHhDZS9pWFFmNy9OVldkUFFF?= =?utf-8?B?ZHBtN1E2UlpMMnhPK21pK0lKR1ZPL3luelVEY1BIdzZCNDZYWUlCMG9aTDY4?= =?utf-8?B?YWdweWZVSldqa0NkMjh3dDlpd1BRWk9FbFpTQ0dlNmo2dXVmNUQzbmJ4bTQr?= =?utf-8?B?VTRtd3BsQ0VuS1FxYTVHQnF6VWNkNjF6Y2w2YnI4Y2V5bTRHZGZPWlNiMUlz?= =?utf-8?B?NEZleXZnMUhrTk1HSW1kS2pCdmZPZjVNbGpJeXNEZXhsWFJ1R0p5VUpjWkx1?= =?utf-8?B?MGx5VTNuZDhWNUZOLzNDWHNXWUxuVEFTVkpIdE8wQkdUZjJHTVNvOURYZDI5?= =?utf-8?B?cStiNGR5R0hNZG9DTDIrN3JuZUk4dW91bC9yMXJCWDk3SDk5UnR4eXd1bmcw?= =?utf-8?B?TjVId1h1NHU3OTdjV3BITFl2Ym91a1dHMXByN25tSHh1LzZ1T0JjM1dtQjhQ?= =?utf-8?B?RWRmTUMrVWZ0QUxaaWRTampRN3N1MEJ0eEJGL3B2ZjNZNUxRbVdqRUJxcUlT?= =?utf-8?B?RHp1WFlKZ3hobis1anpzZG9pTk1qMkYvajBDWEVGeGtIZi9qa1lDT0lQcHVU?= =?utf-8?B?Ym0vN2ZMT0tEOExIa1NFVEdQK2g1VlA4a1ZJUT09?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2025 17:04:50.7206 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37b0a036-9914-4b32-b722-08ddc5540b00 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9107 From: Shay Drory When NR_CPUS is set to 8192 or higher, the current implementation that allocates struct cpu_mask on the stack leads to a compiler warning about the frame size[1]. This patch addresses the issue by moving the allocation of struct cpu_mask to the heap. [1] drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c: In function =E2=80= =98irq_pool_request_irq=E2=80=99: drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c:70:1: warning: the frame size of 1048 bytes is larger than 1024 bytes [-Wframe-larger-than=3D] 70 | } | ^ drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c: In function =E2=80=98mlx= 5_ctrl_irq_request=E2=80=99: drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c:478:1: warning: the frame size of 1040 bytes is larger than 1024 bytes [-Wframe-larger-than=3D] 478 | } | ^ drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c: In function =E2=80=98mlx= 5_irq_request_vector=E2=80=99: drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c:597:1: warning: the frame size of 1040 bytes is larger than 1024 bytes [-Wframe-larger-than=3D] 597 | } | ^ drivers/net/ethernet/mellanox/mlx5/core/eq.c: In function =E2=80=98comp_irq= _request_sf=E2=80=99: drivers/net/ethernet/mellanox/mlx5/core/eq.c:925:1: warning: the frame size of 1064 bytes is larger than 1024 bytes [-Wframe-larger-than=3D] 925 | } | ^ drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c: In function =E2=80= =98irq_pool_request_irq=E2=80=99: drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c:74:1: warning: the frame size of 1048 bytes is larger than 1024 bytes [-Wframe-larger-than=3D] 74 | } | ^ Signed-off-by: Shay Drory Reported-by: Arnd Bergmann Closes: https://lore.kernel.org/all/20250620111010.3364606-1-arnd@kernel.org Reviewed-by: Maher Sanalla Reviewed-by: Moshe Shemesh Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eq.c | 19 +++++++--- .../mellanox/mlx5/core/irq_affinity.c | 21 ++++++++--- .../net/ethernet/mellanox/mlx5/core/pci_irq.c | 37 +++++++++++++------ 3 files changed, 53 insertions(+), 24 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/eth= ernet/mellanox/mlx5/core/eq.c index 66dce17219a6..779efc186255 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -876,19 +876,25 @@ static int comp_irq_request_sf(struct mlx5_core_dev *= dev, u16 vecidx) { struct mlx5_irq_pool *pool =3D mlx5_irq_table_get_comp_irq_pool(dev); struct mlx5_eq_table *table =3D dev->priv.eq_table; - struct irq_affinity_desc af_desc =3D {}; + struct irq_affinity_desc *af_desc; struct mlx5_irq *irq; =20 /* In case SF irq pool does not exist, fallback to the PF irqs*/ if (!mlx5_irq_pool_is_sf_pool(pool)) return comp_irq_request_pci(dev, vecidx); =20 - af_desc.is_managed =3D false; - cpumask_copy(&af_desc.mask, cpu_online_mask); - cpumask_andnot(&af_desc.mask, &af_desc.mask, &table->used_cpus); - irq =3D mlx5_irq_affinity_request(dev, pool, &af_desc); - if (IS_ERR(irq)) + af_desc =3D kzalloc(sizeof(*af_desc), GFP_KERNEL); + if (!af_desc) + return -ENOMEM; + + af_desc->is_managed =3D false; + cpumask_copy(&af_desc->mask, cpu_online_mask); + cpumask_andnot(&af_desc->mask, &af_desc->mask, &table->used_cpus); + irq =3D mlx5_irq_affinity_request(dev, pool, af_desc); + if (IS_ERR(irq)) { + kfree(af_desc); return PTR_ERR(irq); + } =20 cpumask_or(&table->used_cpus, &table->used_cpus, mlx5_irq_get_affinity_ma= sk(irq)); mlx5_core_dbg(pool->dev, "IRQ %u mapped to cpu %*pbl, %u EQs on this irq\= n", @@ -896,6 +902,7 @@ static int comp_irq_request_sf(struct mlx5_core_dev *de= v, u16 vecidx) cpumask_pr_args(mlx5_irq_get_affinity_mask(irq)), mlx5_irq_read_locked(irq) / MLX5_EQ_REFS_PER_IRQ); =20 + kfree(af_desc); return xa_err(xa_store(&table->comp_irqs, vecidx, irq, GFP_KERNEL)); } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c b/drive= rs/net/ethernet/mellanox/mlx5/core/irq_affinity.c index 2691d88cdee1..d0a845579d33 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c @@ -47,29 +47,38 @@ static int cpu_get_least_loaded(struct mlx5_irq_pool *p= ool, static struct mlx5_irq * irq_pool_request_irq(struct mlx5_irq_pool *pool, struct irq_affinity_desc = *af_desc) { - struct irq_affinity_desc auto_desc =3D {}; + struct irq_affinity_desc *auto_desc; struct mlx5_irq *irq; u32 irq_index; int err; =20 + auto_desc =3D kzalloc(sizeof(*auto_desc), GFP_KERNEL); + if (!auto_desc) + return ERR_PTR(-ENOMEM); + err =3D xa_alloc(&pool->irqs, &irq_index, NULL, pool->xa_num_irqs, GFP_KE= RNEL); - if (err) - return ERR_PTR(err); + if (err) { + irq =3D ERR_PTR(err); + goto out; + } if (pool->irqs_per_cpu) { if (cpumask_weight(&af_desc->mask) > 1) /* if req_mask contain more then one CPU, set the least loadad CPU * of req_mask */ cpumask_set_cpu(cpu_get_least_loaded(pool, &af_desc->mask), - &auto_desc.mask); + &auto_desc->mask); else cpu_get(pool, cpumask_first(&af_desc->mask)); } irq =3D mlx5_irq_alloc(pool, irq_index, - cpumask_empty(&auto_desc.mask) ? af_desc : &auto_desc, - NULL); + cpumask_empty(&auto_desc->mask) ? + af_desc : auto_desc, NULL); if (IS_ERR(irq)) xa_erase(&pool->irqs, irq_index); + +out: + kfree(auto_desc); return irq; } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/pci_irq.c index 40024cfa3099..ac00aa29e61a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c @@ -470,26 +470,32 @@ void mlx5_ctrl_irq_release(struct mlx5_core_dev *dev,= struct mlx5_irq *ctrl_irq) struct mlx5_irq *mlx5_ctrl_irq_request(struct mlx5_core_dev *dev) { struct mlx5_irq_pool *pool =3D ctrl_irq_pool_get(dev); - struct irq_affinity_desc af_desc; + struct irq_affinity_desc *af_desc; struct mlx5_irq *irq; =20 - cpumask_copy(&af_desc.mask, cpu_online_mask); - af_desc.is_managed =3D false; + af_desc =3D kzalloc(sizeof(*af_desc), GFP_KERNEL); + if (!af_desc) + return ERR_PTR(-ENOMEM); + + cpumask_copy(&af_desc->mask, cpu_online_mask); + af_desc->is_managed =3D false; if (!mlx5_irq_pool_is_sf_pool(pool)) { /* In case we are allocating a control IRQ from a pci device's pool. * This can happen also for a SF if the SFs pool is empty. */ if (!pool->xa_num_irqs.max) { - cpumask_clear(&af_desc.mask); + cpumask_clear(&af_desc->mask); /* In case we only have a single IRQ for PF/VF */ - cpumask_set_cpu(cpumask_first(cpu_online_mask), &af_desc.mask); + cpumask_set_cpu(cpumask_first(cpu_online_mask), + &af_desc->mask); } /* Allocate the IRQ in index 0. The vector was already allocated */ - irq =3D irq_pool_request_vector(pool, 0, &af_desc, NULL); + irq =3D irq_pool_request_vector(pool, 0, af_desc, NULL); } else { - irq =3D mlx5_irq_affinity_request(dev, pool, &af_desc); + irq =3D mlx5_irq_affinity_request(dev, pool, af_desc); } =20 + kfree(af_desc); return irq; } =20 @@ -548,16 +554,23 @@ struct mlx5_irq *mlx5_irq_request_vector(struct mlx5_= core_dev *dev, u16 cpu, { struct mlx5_irq_table *table =3D mlx5_irq_table_get(dev); struct mlx5_irq_pool *pool =3D table->pcif_pool; - struct irq_affinity_desc af_desc; int offset =3D MLX5_IRQ_VEC_COMP_BASE; + struct irq_affinity_desc *af_desc; + struct mlx5_irq *irq; + + af_desc =3D kzalloc(sizeof(*af_desc), GFP_KERNEL); + if (!af_desc) + return ERR_PTR(-ENOMEM); =20 if (!pool->xa_num_irqs.max) offset =3D 0; =20 - af_desc.is_managed =3D false; - cpumask_clear(&af_desc.mask); - cpumask_set_cpu(cpu, &af_desc.mask); - return mlx5_irq_request(dev, vecidx + offset, &af_desc, rmap); + af_desc->is_managed =3D false; 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Miller" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Saeed Mahameed , "Tariq Toukan" , Mark Bloch , , , , Feng Liu Subject: [PATCH net-next 3/3] net/mlx5e: Expose TIS via devlink tx reporter diagnose Date: Thu, 17 Jul 2025 20:03:12 +0300 Message-ID: <1752771792-265762-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752771792-265762-1-git-send-email-tariqt@nvidia.com> References: <1752771792-265762-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB77:EE_|CY5PR12MB6081:EE_ X-MS-Office365-Filtering-Correlation-Id: 8265839b-81e0-418d-5ca0-08ddc5540d5a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?+mjFiqaN43ESv7gUKAdonZeYu3any9Z8b18o+bbs2U7P8x2BQg6jwAYD8zT2?= =?us-ascii?Q?JlhLPPXI95gscEf1WRKoLo9RbOa4JFoan1ejuQEpVOx/D6WBViLv1lYPwsNo?= =?us-ascii?Q?0Dv7M5rDaXpPWNQClseL+g5oJFLHZhzWyDPIyOKwdkS516/1R7f+vMqCunG6?= =?us-ascii?Q?XQ39JvWVn8XksDk6sRMIp+1FPbEABc3pq2OCAtn3rtLpeo+ceUYIj72Rzs7n?= =?us-ascii?Q?XOuYXAOVOFZLFJ2jCOWe3vruXYEAioRPc4uk1WrFywGvOu/jv4G62QHqE9D9?= =?us-ascii?Q?sKFfk2ab0i3jTNiKJhTjoo3ahu5n5psbJoEnSHsGLtc5eE1w8AGSYMYYYA9J?= =?us-ascii?Q?/0O2VMIWGygX7rr03Q2+fZjjlF1gekVncFzSQ0I2bLLbYo5vO5PoBDrX3KcX?= =?us-ascii?Q?GS9hKDjdmdvohYSNLBXne6myk+L68x6YTnzafZBwB78cXHOJw3ZNkX+1Lq1i?= =?us-ascii?Q?OS20jf064bvIe7Z3eHYDL5MeJIwq/cqcG+eko7+Smpc2+LvDTN/vGiewQl5B?= =?us-ascii?Q?7uqZiX6rJeEbHDspZcCs4bnhGCpzO+f9UgsEego+VRdUFcwM50pMut1IKUF0?= =?us-ascii?Q?hd/VFg/dXH1dwxSwmVeWCYZ+RB+R5julIEj4oZOWCuYmKOaJUkPldQHlwVaC?= =?us-ascii?Q?/KnP+osMdxGE4OUiJ6S9kIi/iZ8t6eQifKitS6Y6vu/uvvmgQ3ssRAuuFNfs?= =?us-ascii?Q?5c5mmvbLuplxbgRStDXciKdTjge7dT5iPv3aTUy+Pe9pIoci/yjF39gz6Igu?= =?us-ascii?Q?LsBMp+UcB4K0f8ibvgu33CCCcDWSJxiFR1Fnlzc52RVZrsEVnmJ3OP/w01+5?= =?us-ascii?Q?M1A0ULmughX0wSInDAO98X5BEXhvxyE0XCcRrYL2qtv6IHDd0b8OTMThd+jv?= =?us-ascii?Q?6OA9ZeUV/7vNnL7UKWjJSqsC2FXLHg/HIDKGl5DVEeKpt+QoDzDDx9bIlY9x?= =?us-ascii?Q?IbfCYGnCAosPcHSk1SbNX/xY9OvPvW7DG3xHoQU/aitAGZIZAlDoF01KDw7W?= =?us-ascii?Q?SAy0aN/O4E1J0MR+2TUyNoQx5biNMBJzj2OvtOmvVOMqyVKAudkChlP7s57c?= =?us-ascii?Q?KtDRy5z6oh3oTNNBAsF8NIG0Dv0RA94ffWgXAUNVBciL/CpzQIznw2E1iB1H?= =?us-ascii?Q?V/dlznv+nN7IwtskvqH3r9DRSjZ+wxwtUGrRaRLK+tDobWwUJ1u/kQpGSFwB?= =?us-ascii?Q?rwGMDb1qhztkoC5upyPKP+oleB3n7kmHh1TYxWMn6Xxpvqx9BxVeo08czVKk?= =?us-ascii?Q?GV1r6Sxulx7T451rv/fmIoaNw0dj0oKmro38gqY7bg+wnMeYQ8XMTF316qWm?= =?us-ascii?Q?1W69zw0L1XKlgcjZYk4iD+Is1tyEwEbZNXTtjjWOImMCQlqB5QMN499ScJAG?= =?us-ascii?Q?Ienq+i5tJRvx8dR5DIDUPaCvdq5P7EzJCnxP8iMsUJ90oI3RhYoljB/vgmqZ?= =?us-ascii?Q?4DFqwqp3jLOhTkZNkXxkZFVNOoVbs0I8Sz5ovSSMUv4J6QQZAith2yNTAl5+?= =?us-ascii?Q?R/27whA5/diTzVLuZRJphil2voCQf2sGI9/Z?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2025 17:04:54.6552 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8265839b-81e0-418d-5ca0-08ddc5540d5a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB77.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6081 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Feng Liu Underneath "TIS Config" tag expose TIS diagnostic information. Expose the tisn of each TC under each lag port. $ sudo devlink health diagnose auxiliary/mlx5_core.eth.2/131072 reporter tx ...... TIS Config: lag port: 0 tc: 0 tisn: 0 lag port: 1 tc: 0 tisn: 8 ...... Signed-off-by: Feng Liu Reviewed-by: Aya Levin Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en/reporter_tx.c | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c b/dri= vers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c index bd96988e102c..85d5cb39b107 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c @@ -311,6 +311,30 @@ mlx5e_tx_reporter_diagnose_common_config(struct devlin= k_health_reporter *reporte mlx5e_health_fmsg_named_obj_nest_end(fmsg); } =20 +static void +mlx5e_tx_reporter_diagnose_tis_config(struct devlink_health_reporter *repo= rter, + struct devlink_fmsg *fmsg) +{ + struct mlx5e_priv *priv =3D devlink_health_reporter_priv(reporter); + u8 num_tc =3D mlx5e_get_dcb_num_tc(&priv->channels.params); + u32 tc, i, tisn; + + devlink_fmsg_arr_pair_nest_start(fmsg, "TIS Config"); + for (i =3D 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) { + for (tc =3D 0; tc < num_tc; tc++) { + tisn =3D mlx5e_profile_get_tisn(priv->mdev, priv, + priv->profile, i, tc); + + devlink_fmsg_obj_nest_start(fmsg); + devlink_fmsg_u32_pair_put(fmsg, "lag port", i); + devlink_fmsg_u32_pair_put(fmsg, "tc", tc); + devlink_fmsg_u32_pair_put(fmsg, "tisn", tisn); + devlink_fmsg_obj_nest_end(fmsg); + } + } + devlink_fmsg_arr_pair_nest_end(fmsg); +} + static int mlx5e_tx_reporter_diagnose(struct devlink_health_reporter *repo= rter, struct devlink_fmsg *fmsg, struct netlink_ext_ack *extack) @@ -326,6 +350,7 @@ static int mlx5e_tx_reporter_diagnose(struct devlink_he= alth_reporter *reporter, goto unlock; =20 mlx5e_tx_reporter_diagnose_common_config(reporter, fmsg); + mlx5e_tx_reporter_diagnose_tis_config(reporter, fmsg); devlink_fmsg_arr_pair_nest_start(fmsg, "SQs"); =20 for (i =3D 0; i < priv->channels.num; i++) { --=20 2.31.1