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Thu, 17 Jul 2025 05:06:28 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Saeed Mahameed , "Tariq Toukan" , Mark Bloch , , , , Chiara Meiohas , "Vlad Dumitrescu" Subject: [PATCH net 1/2] net/mlx5: Fix memory leak in cmd_exec() Date: Thu, 17 Jul 2025 15:06:09 +0300 Message-ID: <1752753970-261832-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752753970-261832-1-git-send-email-tariqt@nvidia.com> References: <1752753970-261832-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F6:EE_|IA0PR12MB8325:EE_ X-MS-Office365-Filtering-Correlation-Id: 793f280f-b3bb-43d8-a9b7-08ddc52a616e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?AFRFUBt1pUGQ7v+J87k9sDmAHEWLnQ9N7IJKtSd/JxRPNAthLpN5FuV1SMFq?= =?us-ascii?Q?9eM93heVwt8dALkdP+jgqp5uVBTP2txQfnQo5IxEIU3tI2LsULtKM/cObgro?= =?us-ascii?Q?oKTuMCQVZuumeUnRoVZ5bwfuP/+0aFcFC13Y+4CWZ7j8eRXjPgbUjw0TrDIj?= =?us-ascii?Q?3b3LDsh0z9VAmuNsjUj4Srwu7w+mTiLKKs+1KuYsAnXt56bp0KZ3lk95hd4E?= =?us-ascii?Q?rdVRdngE8q6GhewwzENCV7MTCkD3ANwDTIUATbGBbo7AWDI6goX/9OpeubFn?= =?us-ascii?Q?QuG9kVNVnuZ+4k/Fas3AlZRZijnjijVkYYz6RiNeoOJ0FXKF9h++U802w/+O?= =?us-ascii?Q?MHhCEYl3OFWhxAi5W2shbybhYgOduHwZ2kcPK3h3Az7jYEvJ8jbxumqvEln9?= =?us-ascii?Q?+Iyd96NwgGE3AYNITSt2r+YMzMec2IV/1KSILI6FyzK71yM+VJgfNPxIHDUp?= =?us-ascii?Q?trWDsxfRgSWUiwT6HER3eXrOb5u6l18X3KAqJh1vXlRVnq9YO2aXyQqhMtam?= =?us-ascii?Q?oB0vQywjMCcmCNBHRuvxTgM2piBeDd/gZNwNVJ0uJie/y18e/KJ8U/rVPFLz?= =?us-ascii?Q?1OWbDEzmDrymg52cL7RkWJutr1Bfe7Kqb0uFKmxouVogKU4tYXKTPi3iutDe?= =?us-ascii?Q?0LBUOiGW117xvxlF6/X7vYrL1iYrCtO8YFXrFS7gEnQrGY/4ujD04GJXWmGP?= =?us-ascii?Q?45vuZFS0MMFKIFKPrdDiD7krEjf7iexbr8e6KM4k5fMTNRzqRkZhLaBGfUc7?= =?us-ascii?Q?P2zHG672m4PdZXOsl68yb/LcpJ5FICk5ETKn2vMyJP2zPOvOfeFISG5i3Lyp?= =?us-ascii?Q?5LY7PoNs4cjUb6arB1hy0gTJ8rt7q4W4wR+T16LMQwQIra+C2Mb7Hj8geNV3?= =?us-ascii?Q?hTmxr+gn7ejF7rNY225wcnkx0GNuAKbCoymxcQujffHMZwyT4O/RmPMBHWJy?= =?us-ascii?Q?9pinRKUOa7H5uB57BY11RVyF/AiZ0J4wdOAHsMXzzejArk2F8OFVqDnKfIHl?= =?us-ascii?Q?6T4B9xbv68aU9Bt8G/fpRgmhQU/TO0+dxr4rWSaeqWjxfRlGF6V4PL83MUyU?= =?us-ascii?Q?Ql8Pap4Fv/DFa3PFMbZUDIHpPYIciCJzI8uICRRzcHZafYVk2nhDiezqOlGo?= =?us-ascii?Q?L1DNTkzKkvUZyxg8Dct16YUYQMngtnx4D5HoRCLDc+B2MdbkMuaoNCIOa2pJ?= =?us-ascii?Q?4Jk9UeKOwyFanva9/7gt8bBf/RSSzFmGRz4F+Uers7f9uSekiS8OdW3hrFJ8?= =?us-ascii?Q?qZYwtE/Ijsyo8VQmxXbSZxLDVJaHz9udTQkA7aCcZQIzO+Q1MuoBIfSG3/+g?= =?us-ascii?Q?qGZjH2+jZWjKd/Lj6Gd6hqVFJK0uSE8Q0c6ieYVe7/XI47TE5byVxULasBsz?= =?us-ascii?Q?KU8OSAx7zWrUzzVl81kcNjXF08YkOGLOSDUPW2Ajv50wWb0gcdS4ZX3gActh?= =?us-ascii?Q?fUJpoCwU1W7oXxQA+kpe0ecppt6teU889+mKTvjBYbSNupcKnbPM/HkEbOKX?= =?us-ascii?Q?DtsOcdkcaI+d2G7xXeJWXwjGw4FMbaBbVkvm?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2025 12:06:37.0217 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 793f280f-b3bb-43d8-a9b7-08ddc52a616e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8325 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chiara Meiohas If cmd_exec() is called with callback and mlx5_cmd_invoke() returns an error, resources allocated in cmd_exec() will not be freed. Fix the code to release the resources if mlx5_cmd_invoke() returns an error. Fixes: f086470122d5 ("net/mlx5: cmdif, Return value improvements") Reported-by: Alex Tereshkin Signed-off-by: Chiara Meiohas Reviewed-by: Moshe Shemesh Signed-off-by: Vlad Dumitrescu Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/cmd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c b/drivers/net/et= hernet/mellanox/mlx5/core/cmd.c index b1aeea7c4a91..e395ef5f356e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c @@ -1947,8 +1947,8 @@ static int cmd_exec(struct mlx5_core_dev *dev, void *= in, int in_size, void *out, =20 err =3D mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context, pages_queue, token, force_polling); - if (callback) - return err; + if (callback && !err) + return 0; =20 if (err > 0) /* Failed in FW, command didn't execute */ err =3D deliv_status_to_err(err); --=20 2.31.1 From nobody Mon Oct 6 19:06:22 2025 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2050.outbound.protection.outlook.com [40.107.96.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6430A29E10A; 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Miller" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Saeed Mahameed , "Tariq Toukan" , Mark Bloch , , , , Shahar Shitrit Subject: [PATCH net 2/2] net/mlx5: E-Switch, Fix peer miss rules to use peer eswitch Date: Thu, 17 Jul 2025 15:06:10 +0300 Message-ID: <1752753970-261832-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752753970-261832-1-git-send-email-tariqt@nvidia.com> References: <1752753970-261832-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231C:EE_|CH3PR12MB8877:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c0566cd-5159-43b0-7087-08ddc52a6409 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?hA4EBnuUix9p4VNcVNvxn+tnUElVEPuahjTOheTazjEx5WK6LUSY2Qc0uJ08?= =?us-ascii?Q?+bIjVvUtFwhDe4SEML7Ch9Yy3xULmWgoarYOZQqoBEx7TiN80zL3OUVDnDmr?= =?us-ascii?Q?4tgdoSjUiWGcyJ43L+f4ZWeX4QjYd93mqHjAMA7I3TnewW09YUZ0q42lksZr?= =?us-ascii?Q?aAV/uj2nD8CTqv29PcsiOUArJEsAXmPmwg2Ox46j/pgJp2+hSIdCqbrTfuA6?= =?us-ascii?Q?MvdtmUPwbZ/TTeDj6ni3ItaKgLxyghB2pqTO+9uq8Mv87zQj9ImgAYYlNUSy?= =?us-ascii?Q?2Zl4l2BHVkJhAEBm7ZPyIMSOmEOm6p/Tcdfa/N2dlV47PdV2AGHNrb3bhcok?= =?us-ascii?Q?GkTPFzl2kVhner9nRqPkc1jEBYk3WT6yRzXHIg7x09uhupaBDD4UKyuE+NBC?= =?us-ascii?Q?TS4gmpPndb6t/jx3ytqQWjtebRSI9yo0ryPuGaN0YT6lby2tgmz+8meydflY?= =?us-ascii?Q?OdNpDehAxZZy6zvPR3wa7zOc67m7QH9qG6pbaQTu+MLFYYgXW3UtRjVPTkyS?= =?us-ascii?Q?dAoXSczx1muY08zMhNRYygDeTlZgt0UrtxD72O5t2iTmmjStZsWk+lCRDQhv?= =?us-ascii?Q?rXFqdCzmbw6BH21SCB5QcrGzLObTtz8sVixMEzfPZRWg/vx0IztkRrV1qdp5?= =?us-ascii?Q?07kq8SBP8Q32aeSJobRA0gTxN9HCTI86PNzRhgX1H5dghvCKsOmv9hzlietW?= =?us-ascii?Q?blTZlLtQ2PK7y1VOSBr3BviHByh1fgP4ldVx9Kb+3kfef2qbRxoVynsL4QmG?= =?us-ascii?Q?2Fi2StDkxKqhtdfp59vvZ+OzB7A8pWppspqpGOY014aTxWAZ+9AkfuKz/fPM?= =?us-ascii?Q?5Ipf9O3FGDKGjBb6CYxQAsVqdIoQf+BzsQDidzfGvHdkvtOaBxhn+C1drJ9F?= =?us-ascii?Q?Yu62PwlrZK/g8cvQE5d0ZynkLcbjuBuZty9lDcqJNdj2DrLXbAMr6sUbwYj+?= =?us-ascii?Q?tfe1PGhhh1Zl4NEE+8QuhMHuCSafop3NVmIxXmQa99K4Q6EvFCnLqXlKdG+L?= =?us-ascii?Q?n/oBfPYiP9qXYGRa9rUsLDWdBfDa7nWb/d5rGpc4j8fcZ8NLxpQ1NBA5wQUo?= =?us-ascii?Q?eC66HX/Hc0gdqUq2mC4te+gXfej5u52f0vMaVTKFOhVyepVux28l8N9qCWwJ?= =?us-ascii?Q?8e/l1CyT0OYMEkhDaM/2Le+eqvWFZUpslvCM8cJiKiDz2MCjnpmQYYovAqw6?= =?us-ascii?Q?IiqFDmJXh3rncSi4Tc2/Ptl5rjklNODvG/unfvSBzf2MnFZD70UAgTL1H0J5?= =?us-ascii?Q?h3obrE5C52KHQ+SbyFOvgLW2QV54EsN/0H/2lc+iBtgh8fjapXcz5wCePqqT?= =?us-ascii?Q?WPUZ/5dKdy6E1IUtZIxkJOsB8Ap+2wuAd6jX+KGTNz8EAWKeGBqIsTB+GwU8?= =?us-ascii?Q?BgBlWoc9TKkY4o5WGEmm3Lj9Q/qhbyJb+3Qn4IMtCX4X500fIga4n04huUW1?= =?us-ascii?Q?49vFdZPa7cMC1XfX/g31f9VZ4a2psEi9n6IyK8jMmoOAx15qZU5a3L547ReI?= =?us-ascii?Q?UAqUptKx++6zaDOfCU2mBDZg04l5fVDOIKlN?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2025 12:06:41.3928 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c0566cd-5159-43b0-7087-08ddc52a6409 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8877 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Shahar Shitrit In the original design, it is assumed local and peer eswitches have the same number of vfs. However, in new firmware, local and peer eswitches can have different number of vfs configured by mlxconfig. In such configuration, it is incorrect to derive the number of vfs from the local device's eswitch. Fix this by updating the peer miss rules add and delete functions to use the peer device's eswitch and vf count instead of the local device's information, ensuring correct behavior regardless of vf configuration differences. Fixes: ac004b832128 ("net/mlx5e: E-Switch, Add peer miss rules") Signed-off-by: Shahar Shitrit Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- .../mellanox/mlx5/core/eswitch_offloads.c | 108 +++++++++--------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 0e3a977d5332..bee906661282 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -1182,19 +1182,19 @@ static void esw_set_peer_miss_rule_source_port(stru= ct mlx5_eswitch *esw, static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw, struct mlx5_core_dev *peer_dev) { + struct mlx5_eswitch *peer_esw =3D peer_dev->priv.eswitch; struct mlx5_flow_destination dest =3D {}; struct mlx5_flow_act flow_act =3D {0}; struct mlx5_flow_handle **flows; - /* total vports is the same for both e-switches */ - int nvports =3D esw->total_vports; struct mlx5_flow_handle *flow; + struct mlx5_vport *peer_vport; struct mlx5_flow_spec *spec; - struct mlx5_vport *vport; int err, pfindex; unsigned long i; void *misc; =20 - if (!MLX5_VPORT_MANAGER(esw->dev) && !mlx5_core_is_ecpf_esw_manager(esw->= dev)) + if (!MLX5_VPORT_MANAGER(peer_dev) && + !mlx5_core_is_ecpf_esw_manager(peer_dev)) return 0; =20 spec =3D kvzalloc(sizeof(*spec), GFP_KERNEL); @@ -1203,7 +1203,7 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_es= witch *esw, =20 peer_miss_rules_setup(esw, peer_dev, spec, &dest); =20 - flows =3D kvcalloc(nvports, sizeof(*flows), GFP_KERNEL); + flows =3D kvcalloc(peer_esw->total_vports, sizeof(*flows), GFP_KERNEL); if (!flows) { err =3D -ENOMEM; goto alloc_flows_err; @@ -1213,10 +1213,10 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_= eswitch *esw, misc =3D MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); =20 - if (mlx5_core_is_ecpf_esw_manager(esw->dev)) { - vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); - esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch, - spec, MLX5_VPORT_PF); + if (mlx5_core_is_ecpf_esw_manager(peer_dev)) { + peer_vport =3D mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF); + esw_set_peer_miss_rule_source_port(esw, peer_esw, spec, + MLX5_VPORT_PF); =20 flow =3D mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw), spec, &flow_act, &dest, 1); @@ -1224,11 +1224,11 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_= eswitch *esw, err =3D PTR_ERR(flow); goto add_pf_flow_err; } - flows[vport->index] =3D flow; + flows[peer_vport->index] =3D flow; } =20 - if (mlx5_ecpf_vport_exists(esw->dev)) { - vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF); + if (mlx5_ecpf_vport_exists(peer_dev)) { + peer_vport =3D mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_ECPF); MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF); flow =3D mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw), spec, &flow_act, &dest, 1); @@ -1236,13 +1236,14 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_= eswitch *esw, err =3D PTR_ERR(flow); goto add_ecpf_flow_err; } - flows[vport->index] =3D flow; + flows[peer_vport->index] =3D flow; } =20 - mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) { + mlx5_esw_for_each_vf_vport(peer_esw, i, peer_vport, + mlx5_core_max_vfs(peer_dev)) { esw_set_peer_miss_rule_source_port(esw, - peer_dev->priv.eswitch, - spec, vport->vport); + peer_esw, + spec, peer_vport->vport); =20 flow =3D mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw), spec, &flow_act, &dest, 1); @@ -1250,22 +1251,22 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_= eswitch *esw, err =3D PTR_ERR(flow); goto add_vf_flow_err; } - flows[vport->index] =3D flow; + flows[peer_vport->index] =3D flow; } =20 - if (mlx5_core_ec_sriov_enabled(esw->dev)) { - mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->d= ev)) { - if (i >=3D mlx5_core_max_ec_vfs(peer_dev)) - break; - esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch, - spec, vport->vport); + if (mlx5_core_ec_sriov_enabled(peer_dev)) { + mlx5_esw_for_each_ec_vf_vport(peer_esw, i, peer_vport, + mlx5_core_max_ec_vfs(peer_dev)) { + esw_set_peer_miss_rule_source_port(esw, peer_esw, + spec, + peer_vport->vport); flow =3D mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec, &flow_act, &dest, 1); if (IS_ERR(flow)) { err =3D PTR_ERR(flow); goto add_ec_vf_flow_err; } - flows[vport->index] =3D flow; + flows[peer_vport->index] =3D flow; } } =20 @@ -1282,25 +1283,27 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_= eswitch *esw, return 0; =20 add_ec_vf_flow_err: - mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->de= v)) { - if (!flows[vport->index]) + mlx5_esw_for_each_ec_vf_vport(peer_esw, i, peer_vport, + mlx5_core_max_ec_vfs(peer_dev)) { + if (!flows[peer_vport->index]) continue; - mlx5_del_flow_rules(flows[vport->index]); + mlx5_del_flow_rules(flows[peer_vport->index]); } add_vf_flow_err: - mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) { - if (!flows[vport->index]) + mlx5_esw_for_each_vf_vport(peer_esw, i, peer_vport, + mlx5_core_max_vfs(peer_dev)) { + if (!flows[peer_vport->index]) continue; - mlx5_del_flow_rules(flows[vport->index]); + mlx5_del_flow_rules(flows[peer_vport->index]); } - if (mlx5_ecpf_vport_exists(esw->dev)) { - vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF); - mlx5_del_flow_rules(flows[vport->index]); + if (mlx5_ecpf_vport_exists(peer_dev)) { + peer_vport =3D mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_ECPF); + mlx5_del_flow_rules(flows[peer_vport->index]); } add_ecpf_flow_err: - if (mlx5_core_is_ecpf_esw_manager(esw->dev)) { - vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); - mlx5_del_flow_rules(flows[vport->index]); + if (mlx5_core_is_ecpf_esw_manager(peer_dev)) { + peer_vport =3D mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF); + mlx5_del_flow_rules(flows[peer_vport->index]); } add_pf_flow_err: esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err= ); @@ -1313,37 +1316,34 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_= eswitch *esw, static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw, struct mlx5_core_dev *peer_dev) { + struct mlx5_eswitch *peer_esw =3D peer_dev->priv.eswitch; u16 peer_index =3D mlx5_get_dev_index(peer_dev); struct mlx5_flow_handle **flows; - struct mlx5_vport *vport; + struct mlx5_vport *peer_vport; unsigned long i; =20 flows =3D esw->fdb_table.offloads.peer_miss_rules[peer_index]; if (!flows) return; =20 - if (mlx5_core_ec_sriov_enabled(esw->dev)) { - mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->d= ev)) { - /* The flow for a particular vport could be NULL if the other ECPF - * has fewer or no VFs enabled - */ - if (!flows[vport->index]) - continue; - mlx5_del_flow_rules(flows[vport->index]); - } + if (mlx5_core_ec_sriov_enabled(peer_dev)) { + mlx5_esw_for_each_ec_vf_vport(peer_esw, i, peer_vport, + mlx5_core_max_ec_vfs(peer_dev)) + mlx5_del_flow_rules(flows[peer_vport->index]); } =20 - mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) - mlx5_del_flow_rules(flows[vport->index]); + mlx5_esw_for_each_vf_vport(peer_esw, i, peer_vport, + mlx5_core_max_vfs(peer_dev)) + mlx5_del_flow_rules(flows[peer_vport->index]); =20 - if (mlx5_ecpf_vport_exists(esw->dev)) { - vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF); - mlx5_del_flow_rules(flows[vport->index]); + if (mlx5_ecpf_vport_exists(peer_dev)) { + peer_vport =3D mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_ECPF); + mlx5_del_flow_rules(flows[peer_vport->index]); } =20 - if (mlx5_core_is_ecpf_esw_manager(esw->dev)) { - vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); - mlx5_del_flow_rules(flows[vport->index]); + if (mlx5_core_is_ecpf_esw_manager(peer_dev)) { + peer_vport =3D mlx5_eswitch_get_vport(peer_esw, MLX5_VPORT_PF); + mlx5_del_flow_rules(flows[peer_vport->index]); } =20 kvfree(flows); --=20 2.31.1