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Wed, 16 Jul 2025 07:18:31 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Saeed Mahameed , "Tariq Toukan" , Mark Bloch , , , , Lama Kayal Subject: [PATCH net-next V2 4/6] net/mlx5e: SHAMPO, Cleanup reservation size formula Date: Wed, 16 Jul 2025 17:17:50 +0300 Message-ID: <1752675472-201445-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752675472-201445-1-git-send-email-tariqt@nvidia.com> References: <1752675472-201445-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066E8:EE_|CYYPR12MB8890:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ac787ee-7f6c-4952-a299-08ddc473af20 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?szO2Apf/LENJRpZ1Dsz8HxIS2PlGYikfTHblI1Nndl/uHLcagKIFvG+dKn9x?= =?us-ascii?Q?pv45x+wdXffg9YC1VJZmh6UoOkmHEzjqS33JHj0ybijxDHk77b16PmUyinOe?= =?us-ascii?Q?XxQR0QnWRCNbVnn63TYGrU0/aeLVl3vYlcaZE5jib5qOUlPOc3NgdlV+Rd/i?= =?us-ascii?Q?46VlUpn6XQOuBHhLLKfuQ1Bi4vKXcnAeCkNDT/iE2rrfbblJqHJBCZ5RRDd4?= =?us-ascii?Q?C5Gl9OwkQt9eIJU1KF85HeFPbVwBwfNLBBBpW6PXtV3mzujS5Ptg8agmWcTS?= =?us-ascii?Q?eNtXywKg/GQVyz53cox8lMST+WYyyuQ4c2YnEd+Q3MrGErKwuchiNyGvtKXn?= =?us-ascii?Q?Gc3uAdp6NQ8sgLii+EJkpN3V1ljsJPGPsvX1+72aJl578pXqtgMaztJhM8IA?= =?us-ascii?Q?YyltvVysk0sHTNnvFwiB9wrWzDY+W94VxAyVOTFi66dzAWTZm4GKbAsNMSBJ?= =?us-ascii?Q?cDNZvKHoRmHUsXbdvZMs28f/YFP0Yg9F0DSfVbUpw991csLz6OEc1pVaC/nG?= =?us-ascii?Q?jU3jRew9a8pY1ZCPD2/QxsQbQTeKDoybbBtTL920tRqQyxS/8oRKnAuibqiT?= =?us-ascii?Q?Ldog3ICKvM5OFhRxcMue+Xj/O6/FDFOh2DjoljL5XrsnSyQUDiB5ApsHbDbL?= =?us-ascii?Q?mM0YKiPGPym4dByUA95pFafSqzTraG/yWR7C4N3mbVr+32vwDak3L6hqIzdC?= =?us-ascii?Q?m90XGyKZj39B1AFvlife57PQOMD4zhP3GDKtH+/EWlYUsGv64Vh0ySTYCZkv?= =?us-ascii?Q?DJ8HGfC+aaPy9BDW9wAiV00W3Ck6H9gUAewdduHKG+/YpboOVZBink53Sqp1?= =?us-ascii?Q?OK2INfOpq0F8wlTBWbAF55cFZbVjSSiv8XfywoGcOgOn/yefD8ubIE7CAw3U?= =?us-ascii?Q?d1TIA0doR+5x7nVbh7T9++v5zJphFiOPFjutNsnf9+rqYKCCvthJUl4bnUrC?= =?us-ascii?Q?n3YUXQX2w9dWpQDcEmEHQEbaTRcuVqwIUqYCNUR4GaZFh+emZ0NRtBdJbasv?= =?us-ascii?Q?9h7y1VxSWy90atK/E590CurJVUos0Z1Iu0B/QaZ6N3TQy8oS4DyPOEwbgcbI?= =?us-ascii?Q?ScLfl6QMOnVEwlLdUnAv28E9JEHeh6qmfByrRSDy2flCwhyz/f8LdSIaQTMl?= =?us-ascii?Q?s8KW88suGOkX0ysE5kylaXQzHt7c6GK/HxlMbF7vzidjXjGB4pu2wpH+VHG6?= =?us-ascii?Q?bq+blObgEacOShqIFTuD2+inKLlPI9LOxqkz4Q2bSBUiiy75BhWUK5RhTW85?= =?us-ascii?Q?wvMIPFnIWop84IIPBkD2TcyW0fCt8EdPua8t4em+hXtTIrpR7AUY6Tzz1TAB?= =?us-ascii?Q?2AvqI6UjoGdYMgtuyuhsHGXqgql7HWosR91GGlCks5vY6NF5FC9B98Aht9+q?= =?us-ascii?Q?UYldNIdPwKyVyfj1IyJHHljCfvmECXUYJ9sDnuN8siAZbYCuuyCloyNrSEdZ?= =?us-ascii?Q?g1CVVEm5ITDCA4ZW16k4z59BuFUCtPzep37Mn8O37gN+mbg9izbuCC+atw+s?= =?us-ascii?Q?62yR+jwZ+oXoYYtF94YzQNLBMthREDOLXaUf?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2025 14:18:49.4168 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ac787ee-7f6c-4952-a299-08ddc473af20 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8890 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lama Kayal The reservation size formula can be reduced to a simple evaluation of MLX5E_SHAMPO_WQ_RESRV_SIZE. This leaves mlx5e_shampo_get_log_rsrv_size() with one single use, which can be replaced with a macro for simplicity. Also, function mlx5e_shampo_get_log_rsrv_size() is used only throughout params.c, make it static. Signed-off-by: Lama Kayal Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Michal Swiatkowski --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 5 +-- .../ethernet/mellanox/mlx5/core/en/params.c | 34 +++++++------------ .../ethernet/mellanox/mlx5/core/en/params.h | 4 --- 3 files changed, 15 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 64e69e616b1f..019bc6ca4455 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -85,8 +85,9 @@ struct page_pool; #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX= _HEADER_ENTRY_SIZE) #define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE (PAGE_SHIFT - MLX5E_SHAMPO_LOG= _MAX_HEADER_ENTRY_SIZE) #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64) -#define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024) -#define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096) +#define MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT (12) +#define MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE (16) +#define MLX5E_SHAMPO_WQ_RESRV_SIZE BIT(MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE) =20 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index fc945bce933a..b98973fe2f03 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -420,19 +420,10 @@ u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_cor= e_dev *mdev, return order_base_2(DIV_ROUND_UP(MLX5E_RX_MAX_HEAD, MLX5E_SHAMPO_WQ_BASE_= HEAD_ENTRY_SIZE)); } =20 -u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev, - struct mlx5e_params *params) +static u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5e_params *params) { - return order_base_2(MLX5E_SHAMPO_WQ_RESRV_SIZE / MLX5E_SHAMPO_WQ_BASE_RES= RV_SIZE); -} - -u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev, - struct mlx5e_params *params) -{ - u32 resrv_size =3D BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * - MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE; - - return order_base_2(DIV_ROUND_UP(resrv_size, params->sw_mtu)); + return order_base_2(DIV_ROUND_UP(MLX5E_SHAMPO_WQ_RESRV_SIZE, + params->sw_mtu)); } =20 u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, @@ -834,13 +825,12 @@ static u32 mlx5e_shampo_get_log_cq_size(struct mlx5_c= ore_dev *mdev, struct mlx5e_params *params, struct mlx5e_xsk_param *xsk) { - int rsrv_size =3D BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * - MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE; u16 num_strides =3D BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk= )); - int pkt_per_rsrv =3D BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); + int pkt_per_rsrv =3D BIT(mlx5e_shampo_get_log_pkt_per_rsrv(params)); u8 log_stride_sz =3D mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); int wq_size =3D BIT(mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); int wqe_size =3D BIT(log_stride_sz) * num_strides; + int rsrv_size =3D MLX5E_SHAMPO_WQ_RESRV_SIZE; =20 /* +1 is for the case that the pkt_per_rsrv dont consume the reservation * so we get a filler cqe for the rest of the reservation. @@ -932,10 +922,11 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, =20 MLX5_SET(wq, wq, shampo_enable, true); MLX5_SET(wq, wq, log_reservation_size, - mlx5e_shampo_get_log_rsrv_size(mdev, params)); + MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE - + MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT); MLX5_SET(wq, wq, log_max_num_of_packets_per_reservation, - mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); + mlx5e_shampo_get_log_pkt_per_rsrv(params)); MLX5_SET(wq, wq, log_headers_entry_size, mlx5e_shampo_get_log_hd_entry_size(mdev, params)); lro_timeout =3D @@ -1048,18 +1039,17 @@ u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *m= dev, struct mlx5e_params *params, struct mlx5e_rq_param *rq_param) { - int resv_size =3D BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * - MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE; u16 num_strides =3D BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, NUL= L)); - int pkt_per_resv =3D BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); + int pkt_per_resv =3D BIT(mlx5e_shampo_get_log_pkt_per_rsrv(params)); u8 log_stride_sz =3D mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL); int wqe_size =3D BIT(log_stride_sz) * num_strides; + int rsrv_size =3D MLX5E_SHAMPO_WQ_RESRV_SIZE; u32 hd_per_wqe; =20 /* Assumption: hd_per_wqe % 8 =3D=3D 0. */ - hd_per_wqe =3D (wqe_size / resv_size) * pkt_per_resv; + hd_per_wqe =3D (wqe_size / rsrv_size) * pkt_per_resv; mlx5_core_dbg(mdev, "%s hd_per_wqe =3D %d rsrv_size =3D %d wqe_size =3D %= d pkt_per_resv =3D %d\n", - __func__, hd_per_wqe, resv_size, wqe_size, pkt_per_resv); + __func__, hd_per_wqe, rsrv_size, wqe_size, pkt_per_resv); return hd_per_wqe; } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.h index bd5877acc5b1..919895f64dcd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h @@ -97,10 +97,6 @@ u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5_core_dev *mde= v, struct mlx5e_xsk_param *xsk); u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev, struct mlx5e_params *params); -u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev, - struct mlx5e_params *params); -u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev, - struct mlx5e_params *params); u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_rq_param *rq_param); --=20 2.31.1