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Mon, 14 Jul 2025 22:16:29 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Carolina Jubran Subject: [PATCH net-next 1/3] ptp: Add ioctl commands to expose raw cycle counter values Date: Tue, 15 Jul 2025 08:15:31 +0300 Message-ID: <1752556533-39218-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752556533-39218-1-git-send-email-tariqt@nvidia.com> References: <1752556533-39218-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529F:EE_|PH8PR12MB7181:EE_ X-MS-Office365-Filtering-Correlation-Id: ffc6299f-26a5-4073-54cc-08ddc35ecc49 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?WAHyvlxQ8toKHMFnXHAyRIquYcqIcFGkO+byLORh6P5UtgVCENm2WnbR0BUT?= =?us-ascii?Q?yYX5lFfJO2YfF86r9JXUSBGykbZ0kPinL0hNZwoAlQDr5Y5UFwt22Bs58V0W?= =?us-ascii?Q?euY9lMCqP29kTkVBCcQjaDGsw4t+mLnHj5YeI9CJbdhdTG0+15MqqYmXivFB?= =?us-ascii?Q?n/Sp+TB3b+abmofYko3lwIpG6C8k+4qyUrBZJdqQLSS983bzXEaqZfIn0SVX?= =?us-ascii?Q?T5tlKf8nlm0KZHomBUh6H3p/cd87PErBYsW8OTE2SOBty2DzatMgsnmi48bx?= =?us-ascii?Q?2qr4dRblSRMIgntfubqk1uair3XbCwKH9JwclH9/jlemGFG2FDukUezK1yFT?= =?us-ascii?Q?XGVCcVE+wGhnHa9ca2Y5EfqXhnLk/eig4xB0Ht1TNKCASdiqmyY7Kv0/OQxE?= =?us-ascii?Q?jYShzk2I4eb2HgO8i4yiFcAPdn3n4sx40lsNP1TPle6uiNbntC/S4HST+DbN?= =?us-ascii?Q?xOEC59iiJ0nVz6yTXrHuEDDJG8PaMbXBhzLiCV8DbuGmubjqkvOg6deyEWRg?= =?us-ascii?Q?uxAEII6VjlFPt2uR5aM60SB9NeAR8YwYVhFIeMlivfRhj5a83LNRL/c3GnPL?= =?us-ascii?Q?/sIh6iEeH/opDcGdIm2D5elCzzJJup6UiqN9go3VmFR0Nooum9csc1BaVq3J?= =?us-ascii?Q?vtxPnaMyX5jxZkC420CMQQvNXWGbakB9dXYiMR6xzODYioYzUPR7lsnSvnrY?= =?us-ascii?Q?E8qA7vSozscblxtyD8LdF0rWMv2bbwIS861qkZeamNUfjNN16hF/hVhz42DS?= =?us-ascii?Q?Mf+RAgsdorp9k9u++F7XFujPzFTvRtLCtu2uxEz5gwwcgNy9jvIZ3NmfJW+s?= =?us-ascii?Q?9NgliP34duDVi+HARKsiekDw3CtW1o2eaEZwDYX3GgLKE8FuCiQl6aRIn3Ll?= =?us-ascii?Q?QyALCBVtXdCBisM5XwdmObqRvXmes6CUX+l6JTLMnxI4H//p/Cp5EUdKmaIl?= =?us-ascii?Q?gddDT2uCq0BD9Y7E5/HB2rxSzCoUEv76zNmSzemOJddjxU+8BX22VYGDH1ek?= =?us-ascii?Q?1VDfhK7O3kFawGYU0pNS0GCdoaF52qC6Ma1jKoC4Ybzu9Fse2fAhU9Q1gy1a?= =?us-ascii?Q?4Eu4cE2xXsDsBoQKRbB65iySxCE1Kzq3vbCFZmIeDqgs378BIvIWyov9hDzg?= =?us-ascii?Q?D/tVp1FUUt+YmiS/VsZ1PYkKHOmkgOvjCdMG9NiViA3ISoHDlHhV4ILriK8v?= =?us-ascii?Q?rcFyl+FNX9B8JfSNaNJ0K8N2H3by4wfLS8vAxi7TE4+ZtOupJ59Ryyx91nLv?= =?us-ascii?Q?OZQLvr4zv3Gglo9ud27NjZST2UNL/74t7txMhlKVF0aYV8C6BEwHN8/i1eTT?= =?us-ascii?Q?nKqHBy6y2HisxdV2EnQzKlNUToNj26wOxfElUMorZXJZI0dQvCYdB/AdyAT3?= =?us-ascii?Q?e0IkoWaWXASupUgFEh5RGTT1/dJUO3AkQVQ6fdsvOHEMu9h/GZLL9uH8BxGg?= =?us-ascii?Q?TtZpdWfHR7w3xpnMKu93BGJDub0EvBU2kKRKosaNsuOCJtECO8WCoq+p/Myr?= =?us-ascii?Q?179ax7io7N08CiPZtNTqrDNu0G8tb0wJ/7gs?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2025 05:16:47.6688 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ffc6299f-26a5-4073-54cc-08ddc35ecc49 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7181 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Introduce two new ioctl commands, PTP_SYS_OFFSET_PRECISE_CYCLES and PTP_SYS_OFFSET_EXTENDED_CYCLES, to allow user space to access the raw free-running cycle counter from PTP devices. These ioctls are variants of the existing PRECISE and EXTENDED offset queries, but instead of returning device time in realtime, they return the raw cycle counter value. Signed-off-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/ptp/ptp_chardev.c | 34 ++++++++++++++++++++++++++-------- include/uapi/linux/ptp_clock.h | 4 ++++ 2 files changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/ptp/ptp_chardev.c b/drivers/ptp/ptp_chardev.c index 4ca5a464a46a..e9719f365aab 100644 --- a/drivers/ptp/ptp_chardev.c +++ b/drivers/ptp/ptp_chardev.c @@ -285,17 +285,21 @@ static long ptp_enable_pps(struct ptp_clock *ptp, boo= l enable) return ops->enable(ops, &req, enable); } =20 -static long ptp_sys_offset_precise(struct ptp_clock *ptp, void __user *arg) +typedef int (*ptp_crosststamp_fn)(struct ptp_clock_info *, + struct system_device_crosststamp *); + +static long ptp_sys_offset_precise(struct ptp_clock *ptp, void __user *arg, + ptp_crosststamp_fn crosststamp_fn) { struct ptp_sys_offset_precise precise_offset; struct system_device_crosststamp xtstamp; struct timespec64 ts; int err; =20 - if (!ptp->info->getcrosststamp) + if (!crosststamp_fn) return -EOPNOTSUPP; =20 - err =3D ptp->info->getcrosststamp(ptp->info, &xtstamp); + err =3D crosststamp_fn(ptp->info, &xtstamp); if (err) return err; =20 @@ -313,12 +317,17 @@ static long ptp_sys_offset_precise(struct ptp_clock *= ptp, void __user *arg) return copy_to_user(arg, &precise_offset, sizeof(precise_offset)) ? -EFAU= LT : 0; } =20 -static long ptp_sys_offset_extended(struct ptp_clock *ptp, void __user *ar= g) +typedef int (*ptp_gettimex_fn)(struct ptp_clock_info *, + struct timespec64 *, + struct ptp_system_timestamp *); + +static long ptp_sys_offset_extended(struct ptp_clock *ptp, void __user *ar= g, + ptp_gettimex_fn gettimex_fn) { struct ptp_sys_offset_extended *extoff __free(kfree) =3D NULL; struct ptp_system_timestamp sts; =20 - if (!ptp->info->gettimex64) + if (!gettimex_fn) return -EOPNOTSUPP; =20 extoff =3D memdup_user(arg, sizeof(*extoff)); @@ -346,7 +355,7 @@ static long ptp_sys_offset_extended(struct ptp_clock *p= tp, void __user *arg) struct timespec64 ts; int err; =20 - err =3D ptp->info->gettimex64(ptp->info, &ts, &sts); + err =3D gettimex_fn(ptp->info, &ts, &sts); if (err) return err; =20 @@ -497,11 +506,13 @@ long ptp_ioctl(struct posix_clock_context *pccontext,= unsigned int cmd, =20 case PTP_SYS_OFFSET_PRECISE: case PTP_SYS_OFFSET_PRECISE2: - return ptp_sys_offset_precise(ptp, argptr); + return ptp_sys_offset_precise(ptp, argptr, + ptp->info->getcrosststamp); =20 case PTP_SYS_OFFSET_EXTENDED: case PTP_SYS_OFFSET_EXTENDED2: - return ptp_sys_offset_extended(ptp, argptr); + return ptp_sys_offset_extended(ptp, argptr, + ptp->info->gettimex64); =20 case PTP_SYS_OFFSET: case PTP_SYS_OFFSET2: @@ -523,6 +534,13 @@ long ptp_ioctl(struct posix_clock_context *pccontext, = unsigned int cmd, case PTP_MASK_EN_SINGLE: return ptp_mask_en_single(pccontext->private_clkdata, argptr); =20 + case PTP_SYS_OFFSET_PRECISE_CYCLES: + return ptp_sys_offset_precise(ptp, argptr, + ptp->info->getcrosscycles); + + case PTP_SYS_OFFSET_EXTENDED_CYCLES: + return ptp_sys_offset_extended(ptp, argptr, + ptp->info->getcyclesx64); default: return -ENOTTY; } diff --git a/include/uapi/linux/ptp_clock.h b/include/uapi/linux/ptp_clock.h index 18eefa6d93d6..65f187b5f0d0 100644 --- a/include/uapi/linux/ptp_clock.h +++ b/include/uapi/linux/ptp_clock.h @@ -245,6 +245,10 @@ struct ptp_pin_desc { _IOWR(PTP_CLK_MAGIC, 18, struct ptp_sys_offset_extended) #define PTP_MASK_CLEAR_ALL _IO(PTP_CLK_MAGIC, 19) #define PTP_MASK_EN_SINGLE _IOW(PTP_CLK_MAGIC, 20, unsigned int) +#define PTP_SYS_OFFSET_PRECISE_CYCLES \ + _IOWR(PTP_CLK_MAGIC, 21, struct ptp_sys_offset_precise) +#define PTP_SYS_OFFSET_EXTENDED_CYCLES \ + _IOWR(PTP_CLK_MAGIC, 22, struct ptp_sys_offset_extended) =20 struct ptp_extts_event { struct ptp_clock_time t; /* Time event occurred. */ --=20 2.31.1 From nobody Tue Oct 7 03:50:42 2025 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2040.outbound.protection.outlook.com [40.107.94.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 523672D46DD; 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Signed-off-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 39 +++++++++++++------ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/= net/ethernet/mellanox/mlx5/core/lib/clock.c index cec18efadc73..b1e2deeefc0c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -247,27 +247,24 @@ static bool mlx5_is_ptm_source_time_available(struct = mlx5_core_dev *dev) return !!MLX5_GET(mtptm_reg, out, psta); } =20 -static int mlx5_mtctr_syncdevicetime(ktime_t *device_time, - struct system_counterval_t *sys_counterval, - void *ctx) +static int mlx5_mtctr_read(struct mlx5_core_dev *mdev, + bool real_time_mode, + struct system_counterval_t *sys_counterval, + u64 *device) { u32 out[MLX5_ST_SZ_DW(mtctr_reg)] =3D {0}; u32 in[MLX5_ST_SZ_DW(mtctr_reg)] =3D {0}; - struct mlx5_core_dev *mdev =3D ctx; - bool real_time_mode; - u64 host, device; + u64 host; int err; =20 - real_time_mode =3D mlx5_real_time_mode(mdev); - MLX5_SET(mtctr_reg, in, first_clock_timestamp_request, MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK); MLX5_SET(mtctr_reg, in, second_clock_timestamp_request, real_time_mode ? MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK : - MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER); + MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER); =20 - err =3D mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), MLX5= _REG_MTCTR, - 0, 0); + err =3D mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), + MLX5_REG_MTCTR, 0, 0); if (err) return err; =20 @@ -281,8 +278,26 @@ static int mlx5_mtctr_syncdevicetime(ktime_t *device_t= ime, .cs_id =3D CSID_X86_ART, .use_nsecs =3D true, }; + *device =3D MLX5_GET64(mtctr_reg, out, second_clock_timestamp); + + return 0; +} + +static int mlx5_mtctr_syncdevicetime(ktime_t *device_time, + struct system_counterval_t *sys_counterval, + void *ctx) +{ + struct mlx5_core_dev *mdev =3D ctx; + bool real_time_mode; + u64 device; + int err; + + real_time_mode =3D mlx5_real_time_mode(mdev); + + err =3D mlx5_mtctr_read(mdev, real_time_mode, sys_counterval, &device); + if (err) + return err; =20 - device =3D MLX5_GET64(mtctr_reg, out, second_clock_timestamp); if (real_time_mode) *device_time =3D ns_to_ktime(REAL_TIME_TO_NS(device >> 32, device & U32_= MAX)); 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Mon, 14 Jul 2025 22:16:37 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Carolina Jubran Subject: [PATCH net-next 3/3] net/mlx5: Support getcyclesx and getcrosscycles Date: Tue, 15 Jul 2025 08:15:33 +0300 Message-ID: <1752556533-39218-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752556533-39218-1-git-send-email-tariqt@nvidia.com> References: <1752556533-39218-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F9:EE_|DS0PR12MB7900:EE_ X-MS-Office365-Filtering-Correlation-Id: a2230ed4-b422-44c9-ea5f-08ddc35ed137 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?SENVVW0xd0VNOXVpRGRkalFkUnVXU3hteUpXZXA4dG9lTEVmYjZYc0JiQWhn?= =?utf-8?B?K3M3NFlBWGN1cTFLcktoWGFmSlFkMlZGRE5XU3R3S1o1MTBXaG9yMUlGYWh4?= =?utf-8?B?b0gxa0xIN0NNYjF1aU5yQU9XSVRsS0pQOFlwTDRQWThqMVhvRVVKVFFXT0hK?= =?utf-8?B?WFFNWmY0c25PTWJSVXBiWEZLamQ3eTdPZER3K3k1YWNjWUdoZnBVTkdMZFFD?= =?utf-8?B?YVI5SVdDSHZNbXdUckJOWHNSTzhKenN6SmFnVm00dTNzbUtLTGZpdlovVU1C?= =?utf-8?B?TmlsanMxN2hzVWtCMFgvZ0xGVXp1ZkNwNThGN2RQUlBpaHVOSlBJVVpHTCtW?= =?utf-8?B?Zm1NejlQNUtmcDI0VTU2RXp3UHNSb2lwVTUxbFVFMCtCM2dJWGEvcGRoZXU2?= =?utf-8?B?eUpPVjBLeHEvYW1nS3FGb21qREJoQXQySTZmckg0eDUxRnJaSkxwai8vZHRq?= =?utf-8?B?SDNrVUFDL0ZpYVJDSE9oMDZVYXMzUFEvQVE2dEZJaDFnU1dmOU9ubUZsSjFS?= =?utf-8?B?NzRZMVFwODlNZERFdFQybFVlb3psMVFSaXAzTmU1K3hyUkVWa0JGUTZoYzJE?= =?utf-8?B?VmJoWU9ZNWptUVFIMW0xckhsanpTdmZqNFFsVnQ5R3NMZ0oxanlyMkpnUHZn?= =?utf-8?B?QnluNC9iN2NHSHV2cDNWQWtEK2QzNStRdmRhYTZqMmg1bXdYeUZyVjdGdStm?= =?utf-8?B?bHFCZHlPNDRQQjU5dXZWN25GTG8rTSswTlFqTWNZRUlRZ0dodTVZQ0dlK2RJ?= =?utf-8?B?b3JoZ3NDeFNDaW1NVy9tWUx4c0IyN1QxeS9JaXNKcDhGV2Z2TlBzeUxaZjg1?= =?utf-8?B?alg1MytVcEZzYWtXcUVhVGdwZmRuZWVFOTFiSndVNS84aEh3OU91QkRpOFFt?= =?utf-8?B?NjNHc3RqdnBYZGpqellGZk9XVVIrbGptMGVWekpJbzFnUnVneHIrOGRrMjdN?= =?utf-8?B?YXhVU3VGSzJVZURMM3dzVWY4aVB6dE9LNklTV09lR3NHZnJzQU5nQUlSYXhW?= =?utf-8?B?WFZobzRSSVA0N1BMTU1XeCsvTXNBRFdjQjFSSFZIeDI5QVhLenYwU29MVWJj?= =?utf-8?B?V3htWmxnRGRUY0xITlhLTnY5N2JVWlRJSGJieTJaeDRIVUVQOHd4RjZtdk81?= =?utf-8?B?aVRnbWFSZ0ZXcFg4L0dGMU9FTWdhbUFOSkppSHJZSmdybkxSajRlNS85T2dl?= =?utf-8?B?UU00TURYdSsyUVVBb2IxbmZOMW12dnE3VjFUejhZZFdPYXprUDNsb2NsVnJu?= =?utf-8?B?b1pvTDdDU1MxWHNuVzAxZGpYRG5XWlJFRUxVek1IOFhjTUZaa0VNZDZtck5m?= =?utf-8?B?aHJwbG9YdHBHTXM3Wjg0Nzc2ay9uOXBYbkxxMklZbnA4RnZ3UHB1b3ZWYThn?= =?utf-8?B?cFNsdC9ZRWxLb3VDK2JEd3lVTnY2b2xtY1pTUXpoS1VTY0sybDZaM1E0MU11?= =?utf-8?B?MFlWZUwyZWRVdHhaQlJLSGJ5T1JmbkVFeHR5WlRzZG5iWUlwWlBWYUpmVk9o?= =?utf-8?B?dEZtTVdPZHdkTG9WYmpFZ2lac2RTUDJlTGZWcmlTV3JNQWg0UytSbERDNGJK?= =?utf-8?B?S3RiS2RrODBYenRPNVFkMmk4WXpwZzkwOVkvd2VXWnNjMSt2ZWRpTFJWYWR6?= =?utf-8?B?RmJJQU14OWRyOVZqbURxZXd2MThLaGs0YnJ0dGtNbXgxaWQvaWk3aTBiOVZo?= =?utf-8?B?ZVlFOURiZ1puRTNyZU81VmJKSzQ4MXI2djZXQVhCQk1wSGNoY2FHeldSdWtY?= =?utf-8?B?eUNIMjlyc1JucnJnOFBKa2N4WGt5cC90ZGhMaWduQTFtUGRyYldjN2dKUWR2?= =?utf-8?B?TXA2QmlNUDFMWnFpQjlLNWlZdmpEbEpuK3pEYTNTYy84cFhBT2JUK0F2Z1pn?= =?utf-8?B?ejlHSjJqVE5hTkRaYk9zNXl2b3dTTUUyTXUyMTA3dmVnbjRmbVpyMmd4VURj?= =?utf-8?B?UG92Tk44WVVZcnhMWUpSL2RjOHVYd3NhdWhxV3ZIT0Y5b0pKaGpqTm1LWjlw?= =?utf-8?B?eFZRSjN5dVFFYVNpcUJlMmt6YXhGL28yMkd2b0Y4eGFOME9XRTEwU1V4aXFL?= =?utf-8?Q?DfFxTi?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2025 05:16:55.9460 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2230ed4-b422-44c9-ea5f-08ddc35ed137 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F9.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7900 From: Carolina Jubran Implement the getcyclesx64 and getcrosscycles callbacks in ptp_info to expose the device=E2=80=99s raw free-running counter. Signed-off-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 74 ++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/= net/ethernet/mellanox/mlx5/core/lib/clock.c index b1e2deeefc0c..2f75726674a9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -306,6 +306,23 @@ static int mlx5_mtctr_syncdevicetime(ktime_t *device_t= ime, return 0; } =20 +static int +mlx5_mtctr_syncdevicecyclestime(ktime_t *device_time, + struct system_counterval_t *sys_counterval, + void *ctx) +{ + struct mlx5_core_dev *mdev =3D ctx; + u64 device; + int err; + + err =3D mlx5_mtctr_read(mdev, false, sys_counterval, &device); + if (err) + return err; + *device_time =3D ns_to_ktime(device); + + return 0; +} + static int mlx5_ptp_getcrosststamp(struct ptp_clock_info *ptp, struct system_device_crosststamp *cts) { @@ -330,6 +347,32 @@ static int mlx5_ptp_getcrosststamp(struct ptp_clock_in= fo *ptp, mlx5_clock_unlock(clock); return err; } + +static int mlx5_ptp_getcrosscycles(struct ptp_clock_info *ptp, + struct system_device_crosststamp *cts) +{ + struct mlx5_clock *clock =3D + container_of(ptp, struct mlx5_clock, ptp_info); + struct system_time_snapshot history_begin =3D {0}; + struct mlx5_core_dev *mdev; + int err; + + mlx5_clock_lock(clock); + mdev =3D mlx5_clock_mdev_get(clock); + + if (!mlx5_is_ptm_source_time_available(mdev)) { + err =3D -EBUSY; + goto unlock; + } + + ktime_get_snapshot(&history_begin); + + err =3D get_device_system_crosststamp(mlx5_mtctr_syncdevicecyclestime, + mdev, &history_begin, cts); +unlock: + mlx5_clock_unlock(clock); + return err; +} #endif /* CONFIG_X86 */ =20 static u64 mlx5_read_time(struct mlx5_core_dev *dev, @@ -528,6 +571,24 @@ static int mlx5_ptp_gettimex(struct ptp_clock_info *pt= p, struct timespec64 *ts, return 0; } =20 +static int mlx5_ptp_getcyclesx(struct ptp_clock_info *ptp, + struct timespec64 *ts, + struct ptp_system_timestamp *sts) +{ + struct mlx5_clock *clock =3D container_of(ptp, struct mlx5_clock, + ptp_info); + struct mlx5_core_dev *mdev; + u64 cycles; + + mlx5_clock_lock(clock); + mdev =3D mlx5_clock_mdev_get(clock); + + cycles =3D mlx5_read_time(mdev, sts, false); + *ts =3D ns_to_timespec64(cycles); + mlx5_clock_unlock(clock); + return 0; +} + static int mlx5_ptp_adjtime_real_time(struct mlx5_core_dev *mdev, s64 delt= a) { u32 in[MLX5_ST_SZ_DW(mtutc_reg)] =3D {}; @@ -1244,6 +1305,7 @@ static void mlx5_init_timer_max_freq_adjustment(struc= t mlx5_core_dev *mdev) static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) { struct mlx5_clock *clock =3D mdev->clock; + bool expose_cycles; =20 /* Configure the PHC */ clock->ptp_info =3D mlx5_ptp_clock_info; @@ -1251,12 +1313,22 @@ static void mlx5_init_timer_clock(struct mlx5_core_= dev *mdev) if (MLX5_CAP_MCAM_REG(mdev, mtutc)) mlx5_init_timer_max_freq_adjustment(mdev); =20 + expose_cycles =3D !MLX5_CAP_GEN(mdev, disciplined_fr_counter) || + !mlx5_real_time_mode(mdev); + #ifdef CONFIG_X86 if (MLX5_CAP_MCAM_REG3(mdev, mtptm) && - MLX5_CAP_MCAM_REG3(mdev, mtctr) && boot_cpu_has(X86_FEATURE_ART)) + MLX5_CAP_MCAM_REG3(mdev, mtctr) && boot_cpu_has(X86_FEATURE_ART)) { clock->ptp_info.getcrosststamp =3D mlx5_ptp_getcrosststamp; + if (expose_cycles) + clock->ptp_info.getcrosscycles =3D + mlx5_ptp_getcrosscycles; + } #endif /* CONFIG_X86 */ =20 + if (expose_cycles) + clock->ptp_info.getcyclesx64 =3D mlx5_ptp_getcyclesx; + mlx5_timecounter_init(mdev); mlx5_init_clock_info(mdev); mlx5_init_overflow_period(mdev); --=20 2.31.1