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Miller" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Saeed Mahameed , "Tariq Toukan" , Mark Bloch , , , , Lama Kayal Subject: [PATCH net-next 4/6] net/mlx5e: SHAMPO, Cleanup reservation size formula Date: Mon, 14 Jul 2025 08:39:43 +0300 Message-ID: <1752471585-18053-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752471585-18053-1-git-send-email-tariqt@nvidia.com> References: <1752471585-18053-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002311:EE_|MW3PR12MB4396:EE_ X-MS-Office365-Filtering-Correlation-Id: e7d70f25-50eb-4fa2-5857-08ddc29903b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?rIP2m6QmrHUgzI3z+cF5I6idYwLqE6tpd7cD8RvmZH0KREo4wFQm/jYMItag?= =?us-ascii?Q?khP0cc7dI+NmrOCJWa4gqpvOLi6b+L0ByMHTFDzZFRRtq3OkigYQo1JlfEmA?= =?us-ascii?Q?u+0tsaI9lptB9VADKGir2O72GcWDxOUwq5x651M6ldIV3YO+ReHB3J2w8dnl?= =?us-ascii?Q?JwO8vwzLNeERa4WNfQL4YC75B+teWqvLsixvUWBD9wngXlcYfakVz/TT5+dC?= =?us-ascii?Q?ngOLtYiSNq93zTwqynqYD3ghBKO+MievzgXBidHXWBNNlUM/WmDaqujoJBfy?= =?us-ascii?Q?CNFW0+/X27p98JjbZUPeAq0+bKt0h6gwkDB/8zXrWHq/k2eP6o5OGP2NFof5?= =?us-ascii?Q?O5eMInbSyWEf6DmUsiGXNXGKEWOV3/eTHbPGhdjA/07XsawIemq35iRAb8ym?= =?us-ascii?Q?BfLz2y5jgTTPnmEA/aEWxgQI9qUaItMX0wUTFCAwOSLZvc/ViVqteARCpq7U?= =?us-ascii?Q?B6ck3fKco9gHekzjRHOABEni/Uq4gAZrSUJiTxQkvnz/9h+AH+AWJCS3hMiP?= =?us-ascii?Q?D6x/pWM6bPCzyGU2xxPmU8/sIVDlXq1BHGKZkTOxvLh0AzeEy6fKA2V3s0Kt?= =?us-ascii?Q?6SuE/cMJXdmpMzzDFJOlQq0n7ObFJIoA4s3h8XeEvN928uDpjdwcvyATJNvN?= =?us-ascii?Q?ZeC/6hhz6MOL0gtvpc+ausD04Aoe4zoCNoqy76Thqu400B7io/mdjbpC/JVW?= =?us-ascii?Q?mgUwkA9n5oxCZSTRl1yl4tuo4Nqo4vbyV3dyBT1VSNLqMsS4lOU7A4TucyIX?= =?us-ascii?Q?LBu33m9hk0iW2Bdu81UhzY+B45Oycn3hNO6oRjrTesbpXCJ5eoQhKSkJbPx0?= =?us-ascii?Q?3XU6DEQ2K1B6WCmICc2iAlwS5a35EkdYibZJ6cWKmgqOKrtc5Br2rLIACvAE?= =?us-ascii?Q?YQEpIshJNfHe2R11LEQDT7gi3MCmEn2jomN1Mbdcz9WWHjpUnc+LDCFmqYMv?= =?us-ascii?Q?XC98uidAAU7V9+tK2eCd6zJSU7svnQuNaTgvXIMTdfvqZxECyRhTTLm66v3V?= =?us-ascii?Q?iVA7wqVKIQng9tsfbR143I8slsFmUapbMyCN95MP8lTserCawcjWlCRwMa6J?= =?us-ascii?Q?njmjIA1I6t4StBr29iCDbY1AXpgr50jmSSI1taGB0WppYVGExpnddzyNFMLT?= =?us-ascii?Q?IYSVfDFBYcapJGh4He0aiB1j2rDC26c6NIL9yhaM/bY+CQdZ83/Zr84wG6HB?= =?us-ascii?Q?hiVSaZIcpten/lv8m+94QE1FcSJS2kmV61ZFoCzYh9cx9m57pSvTSqDqplgW?= =?us-ascii?Q?2TLc86NSmTaCKJNKBs9G0uMYNcqGw9lxuKDugOnuNpku4sBL5K0NeeWLDi68?= =?us-ascii?Q?oJ8yXXiHT1HzVTaTDUFFyVsWGAsEa0GWjBsu0pNajpMdqvbw66w+iRF8kPkG?= =?us-ascii?Q?knon7wYk866y/5GjM9v4JrIzjKgqQkRoKLJq63f0GcE7D2yDtnG4WKM4JEn1?= =?us-ascii?Q?5AD9n2Mups8p5f59PsorVcUFv/Tbc9eaNWzaKJmpOkjfL+LYTXhhDZAEibt/?= =?us-ascii?Q?KTtKL25cPAKy4Q1TZcm31baTecCsEDMFvDwa?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2025 05:41:00.4332 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7d70f25-50eb-4fa2-5857-08ddc29903b8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002311.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4396 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lama Kayal The reservation size formula can be reduced to a simple evaluation of MLX5E_SHAMPO_WQ_RESRV_SIZE. This leaves mlx5e_shampo_get_log_rsrv_size() with one single use, which can be replaced with a macro for simplicity. Also, function mlx5e_shampo_get_log_rsrv_size() is used only throughout params.c, make it static. Signed-off-by: Lama Kayal Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Michal Swiatkowski --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 5 +-- .../ethernet/mellanox/mlx5/core/en/params.c | 34 +++++++------------ .../ethernet/mellanox/mlx5/core/en/params.h | 4 --- 3 files changed, 15 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 64e69e616b1f..019bc6ca4455 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -85,8 +85,9 @@ struct page_pool; #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX= _HEADER_ENTRY_SIZE) #define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE (PAGE_SHIFT - MLX5E_SHAMPO_LOG= _MAX_HEADER_ENTRY_SIZE) #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64) -#define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024) -#define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096) +#define MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT (12) +#define MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE (16) +#define MLX5E_SHAMPO_WQ_RESRV_SIZE BIT(MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE) =20 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index fc945bce933a..616251ec6d69 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -420,19 +420,10 @@ u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_cor= e_dev *mdev, return order_base_2(DIV_ROUND_UP(MLX5E_RX_MAX_HEAD, MLX5E_SHAMPO_WQ_BASE_= HEAD_ENTRY_SIZE)); } =20 -u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev, - struct mlx5e_params *params) +static u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5e_params *params) { - return order_base_2(MLX5E_SHAMPO_WQ_RESRV_SIZE / MLX5E_SHAMPO_WQ_BASE_RES= RV_SIZE); -} - -u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev, - struct mlx5e_params *params) -{ - u32 resrv_size =3D BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * - MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE; - - return order_base_2(DIV_ROUND_UP(resrv_size, params->sw_mtu)); + return order_base_2(DIV_ROUND_UP(MLX5E_SHAMPO_WQ_RESRV_SIZE, + params->sw_mtu)); } =20 u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, @@ -834,10 +825,9 @@ static u32 mlx5e_shampo_get_log_cq_size(struct mlx5_co= re_dev *mdev, struct mlx5e_params *params, struct mlx5e_xsk_param *xsk) { - int rsrv_size =3D BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * - MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE; + int rsrv_size =3D MLX5E_SHAMPO_WQ_RESRV_SIZE; u16 num_strides =3D BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk= )); - int pkt_per_rsrv =3D BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); + int pkt_per_rsrv =3D BIT(mlx5e_shampo_get_log_pkt_per_rsrv(params)); u8 log_stride_sz =3D mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); int wq_size =3D BIT(mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); int wqe_size =3D BIT(log_stride_sz) * num_strides; @@ -932,10 +922,11 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, =20 MLX5_SET(wq, wq, shampo_enable, true); MLX5_SET(wq, wq, log_reservation_size, - mlx5e_shampo_get_log_rsrv_size(mdev, params)); + MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE - + MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT); MLX5_SET(wq, wq, log_max_num_of_packets_per_reservation, - mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); + mlx5e_shampo_get_log_pkt_per_rsrv(params)); MLX5_SET(wq, wq, log_headers_entry_size, mlx5e_shampo_get_log_hd_entry_size(mdev, params)); lro_timeout =3D @@ -1048,18 +1039,17 @@ u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *m= dev, struct mlx5e_params *params, struct mlx5e_rq_param *rq_param) { - int resv_size =3D BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * - MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE; + int rsrv_size =3D MLX5E_SHAMPO_WQ_RESRV_SIZE; u16 num_strides =3D BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, NUL= L)); - int pkt_per_resv =3D BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); + int pkt_per_resv =3D BIT(mlx5e_shampo_get_log_pkt_per_rsrv(params)); u8 log_stride_sz =3D mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL); int wqe_size =3D BIT(log_stride_sz) * num_strides; u32 hd_per_wqe; =20 /* Assumption: hd_per_wqe % 8 =3D=3D 0. */ - hd_per_wqe =3D (wqe_size / resv_size) * pkt_per_resv; + hd_per_wqe =3D (wqe_size / rsrv_size) * pkt_per_resv; mlx5_core_dbg(mdev, "%s hd_per_wqe =3D %d rsrv_size =3D %d wqe_size =3D %= d pkt_per_resv =3D %d\n", - __func__, hd_per_wqe, resv_size, wqe_size, pkt_per_resv); + __func__, hd_per_wqe, rsrv_size, wqe_size, pkt_per_resv); return hd_per_wqe; } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.h index bd5877acc5b1..919895f64dcd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h @@ -97,10 +97,6 @@ u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5_core_dev *mde= v, struct mlx5e_xsk_param *xsk); u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev, struct mlx5e_params *params); -u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev, - struct mlx5e_params *params); -u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev, - struct mlx5e_params *params); u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_rq_param *rq_param); --=20 2.40.1