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Thu, 10 Jul 2025 06:54:35 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Saeed Mahameed , "Tariq Toukan" , Mark Bloch , , , , Carolina Jubran Subject: [PATCH net 1/3] net/mlx5: Reset bw_share field when changing a node's parent Date: Thu, 10 Jul 2025 16:53:42 +0300 Message-ID: <1752155624-24095-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752155624-24095-1-git-send-email-tariqt@nvidia.com> References: <1752155624-24095-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003446:EE_|DS7PR12MB8250:EE_ X-MS-Office365-Filtering-Correlation-Id: f3143a0b-0e16-47bd-7ab9-08ddbfb95648 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?YIaSLAdslh40cIlrBa60QGioXSS+0oFJBf9hhuKA2z7ZrssGVZlP2JpcoZxk?= =?us-ascii?Q?GXVj3iGNvNbB4+A2AI1RePZ0nj/dz1BedfqWik6bAWifrcly18IaA6XhW+FQ?= =?us-ascii?Q?CkUKtl8puLTsxphhxVA7hZ92SJcJn0rtW4tlx0hCwuWRX87SGGUnfmOWAcLs?= =?us-ascii?Q?xZxXom7E9+mHnja/tL/cbLRtv1JKVZuagLsMGPrgIbep3QULqX2buWRPRcb6?= =?us-ascii?Q?OHYIZ0xaNUKdO6QCtz5GxjRiu4mWDYxETsBiwnCBHtWERRu03P4fqHSuh+n7?= =?us-ascii?Q?B7Wa2oitweWM0luPTfhPCAPeelqov6MJ9AP/KJ9ICgzoCkZqkrZMYp9VyLlm?= =?us-ascii?Q?tRfZ4XfWnkFn366ZswOxgGEwl+5eGnf0mKUYdc4tBsSFXQZBR0OySreryjdn?= =?us-ascii?Q?0WkY2sP0knDebN+8Usfq3HMoFh786gZddkSKdI62fYxaboeHhjH1L7A3EejF?= =?us-ascii?Q?qJ32bcGC7M8cQHF/uHNXI8CcUFYm2PYzkuzKWLba/mxrLqefwbshIO/GhJth?= =?us-ascii?Q?1yNmNawMh7CGmIDnBwMH4jsn5Y42YdoMC465kTDDuwkaxTN8y345A3eiaJ+J?= =?us-ascii?Q?GQ6p+fQ9KZBGeEq5wFGq1lTRIgr+dy975HdvLXxkNnv53ZdPvJzRxU+FlC2j?= =?us-ascii?Q?lvA+PiDsFPoqVh/IdFqITp0VMoJMVR8+BWWhnkstm3KlXLWQBT7GDyneisCP?= =?us-ascii?Q?SyebGs+t5d2EN51pUH8ZauXW2/738RrqfyLvvl29FLKCdLDEq8NbsbqQoGCp?= =?us-ascii?Q?TI/AKpU0NNOH0vzADljrb6U8M0EOW582lyK75b1rkgubs5idrepz3Wbm1ceX?= =?us-ascii?Q?LMCyEQxv1danezTvaXCZyAtlhTgWpanKF0UcGVYgq/B0jUPpDlFLXEZH3/Ab?= =?us-ascii?Q?vSL3qGOIFoWpGTENKgTBSMzN+sg8k3dfQBbGr+BBXuChlsdv5wZo6DtYOtQH?= =?us-ascii?Q?+zNrQ0rzHpVniOrAQYOCwPg6qfHFzzbTKGwXxW2mtj3gQfWXPjKtGwWFezlz?= =?us-ascii?Q?4ibnB8qkvNvHc18BvYcRHDHajxUkHqjMX+o7D5OZNGWEmCd4/acDADijbX8u?= =?us-ascii?Q?9+Saa2IM3v7jFtzrQkO3on6LLzpIVvKuLUDhJUA4gmZcZD0PvO75PUgnT+TI?= =?us-ascii?Q?pTwhpxuiihQdUry7w3e6jpY/6JHNMntpf207mJxl1m5HnuUafGgkB58JXxJS?= =?us-ascii?Q?hdQw+egdgr8U5maaNM6NyYBbPbz9/Lt7lo/LfmE4K8WBWxF6pFThgrQfO6cc?= =?us-ascii?Q?WOj30OPn9TGv2Uy7C/X/r9vOSV5Rjl6vwE24O2zvl+r1T6/u4xQ+zYDTFVpF?= =?us-ascii?Q?wmVDeCvI8jmoOL7cv3vLZE0/tSj4ow5d1EzIJQwEdErjROGg3CTlgsKFFOOS?= =?us-ascii?Q?qTwwoQ/54wdnFNbluqo74VwDvHzKIj08dOyfAOJAR+moyTPXhNZsUvnOGamn?= =?us-ascii?Q?tavwFs8ZfO3GBH/ByL98YdJIrbcZ1KZd1uvGpXhvrvb+kl4WSaesrFaxClte?= =?us-ascii?Q?kQLZSNA5ci4gPDJFyOAW9GZLksGfCNVFphGn?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 13:54:49.2577 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f3143a0b-0e16-47bd-7ab9-08ddbfb95648 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003446.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8250 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran When changing a node's parent, its scheduling element is destroyed and re-created with bw_share 0. However, the node's bw_share field was not updated accordingly. Set the node's bw_share to 0 after re-creation to keep the software state in sync with the firmware configuration. Fixes: 9c7bbf4c3304 ("net/mlx5: Add support for setting parent of nodes") Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Jacob Keller --- drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index b6ae384396b3..ad9f6fca9b6a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -1076,6 +1076,7 @@ static int esw_qos_vports_node_update_parent(struct m= lx5_esw_sched_node *node, return err; } esw_qos_node_set_parent(node, parent); + node->bw_share =3D 0; =20 return 0; } --=20 2.31.1 From nobody Tue Oct 7 09:52:19 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2076.outbound.protection.outlook.com [40.107.243.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 011AF274FDA; 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Miller" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Saeed Mahameed , "Tariq Toukan" , Mark Bloch , , , , Carolina Jubran Subject: [PATCH net 2/3] net/mlx5e: Fix race between DIM disable and net_dim() Date: Thu, 10 Jul 2025 16:53:43 +0300 Message-ID: <1752155624-24095-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752155624-24095-1-git-send-email-tariqt@nvidia.com> References: <1752155624-24095-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003446:EE_|CH3PR12MB7692:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c669f89-3654-435a-b51b-08ddbfb95890 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?BNNYwiGNinsxKudVW2hVOsos3bpPGdIhTXM9g/TfL9fv4zIfus5VFPdleiow?= =?us-ascii?Q?Yfmmzd50OUCNETNHKyGR4yeNrCGWxfYVk/VV59T1b5vnxe9IG5WZZ0eSKdz4?= =?us-ascii?Q?Lfm2SeC1qtM1QsaBoXVSp30xkPFEUhybWFppTUzQrMZKrfvIj4jZkcyPiDbE?= =?us-ascii?Q?BZ7M6fy0deTQjQRG72orUy4l6tb5zfqJN36YRK4rMiFgg/saXeNJGx5Gm9RC?= =?us-ascii?Q?G12fMXJblo1P9un1Y7WWpkQMFnk6bA9DBrYgOZxi+wQ/kRF/oKlQIL+FCbe2?= =?us-ascii?Q?Ep8o9x3MV0L0x2ILs5W2Yu4gDxjBB5mqO0NNwoye7Qpyn3MSvnvOmTiWucG5?= =?us-ascii?Q?BO2TU1o3aXb27I13krbd446tKlcFXZwL1edokod12Z7mbDv/XeQljRZfxk0P?= =?us-ascii?Q?HWdD44keBqz0FuA3ra+GGAzOFQGWGSDenPUr/ndnCJTAGrUQas+kg2Hdmy21?= =?us-ascii?Q?i0380mlVSmemPy2GW/5Otky7DRgAd2HYiEbEAkePhI27SfNFNrMOJrYRG6+z?= =?us-ascii?Q?O+KAFgGJIUEZUqrHj6I5e76BIchwPim65+KKiiFfSqfX1F/aQhTg9+qLs6Op?= =?us-ascii?Q?Eq+8d8r3lMAsIN0gaQPDG/zwpS3Y8Srck6e36O6DAZyRkZsn88YwLBg9fh/i?= =?us-ascii?Q?EJm7XcW6ZOyCUQooYqtXqXFPwhN2wZEENCrRLIlZNvDUxamT4gWGQ0OKTUAr?= =?us-ascii?Q?h6ZRuk4kOGmN8vWfa9GPxy8Y5U2HO4tdkldDp/PDJ5qcE1/5Y415aiQc6mfL?= =?us-ascii?Q?93iXdJoeSP+B/hparXttGJ3vJMO2AOX2yRvm85JWTmwZQd9iYqc0B+lnIMjK?= =?us-ascii?Q?SY4kRBShW9qBG+jZN0/D380Kc5A7/RLWXNOp4dFfQUTts/FGCK5ikuhUij8G?= =?us-ascii?Q?NWEc+B17KjNGDi+vebe/ttNjmkLD2xDWJ5rZzIAAhIoA6E/uzguow98B+Nqc?= =?us-ascii?Q?GSGsuyx5KobwMgKZvMXnZ2xRwNXSGU5rEzotrqe5Eij9hZkzFfz1gKPmE5LJ?= =?us-ascii?Q?Lpnt22yG0KUr/Ki2Q/l4p2E7eIjOe6R+jS1x61cWxzo+33u439c6L1SIN0I3?= =?us-ascii?Q?SyfR+Xj17z6ZfVSsGn2G2TNmTJc1Zi+xh353Xyr2nJ5JS4jChBk0kOMbkS9x?= =?us-ascii?Q?1MwE9+IlKZuGr9rqHCo+q1OdhHItrnEMynpURX5BPvfFzK1bupWe5mBDbVoj?= =?us-ascii?Q?FRJ7BTxeyMySSZttjWg8rIx0QM+XhN/BNWCNal0e8xeO3+l/aJ481qtvnQQU?= =?us-ascii?Q?SejhS3Y/uCHSl1ISIxUlmewGbMAyidhOkHjBVIAussps3vZ6kWl1hYIZYnGh?= =?us-ascii?Q?qGAn81KIpGpPnkvnsWyUIo3dtRtn9DUYttRdN4xtKRvNs0E36WZUNKt0vHCX?= =?us-ascii?Q?lj40JBDpm+7RYDXdCmCXAR1t2NIDXw5RzXRjByt97C8FtQfe6QWWmknBT5Pb?= =?us-ascii?Q?IvffXYa1WqflK0HZk8b4GjQZQvek0jcuHU21eIuVFiFUmx3bZACrrl+gH8ie?= =?us-ascii?Q?BjmzA3Np3jp4MDuhBj5xkI/Qp4Hj3GyhSHee?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 13:54:53.0894 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c669f89-3654-435a-b51b-08ddbfb95890 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003446.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7692 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran There's a race between disabling DIM and NAPI callbacks using the dim pointer on the RQ or SQ. If NAPI checks the DIM state bit and sees it still set, it assumes `rq->dim` or `sq->dim` is valid. But if DIM gets disabled right after that check, the pointer might already be set to NULL, leading to a NULL pointer dereference in net_dim(). Fix this by calling `synchronize_net()` before freeing the DIM context. This ensures all in-progress NAPI callbacks are finished before the pointer is cleared. Kernel log: BUG: kernel NULL pointer dereference, address: 0000000000000000 ... RIP: 0010:net_dim+0x23/0x190 ... Call Trace: ? __die+0x20/0x60 ? page_fault_oops+0x150/0x3e0 ? common_interrupt+0xf/0xa0 ? sysvec_call_function_single+0xb/0x90 ? exc_page_fault+0x74/0x130 ? asm_exc_page_fault+0x22/0x30 ? net_dim+0x23/0x190 ? mlx5e_poll_ico_cq+0x41/0x6f0 [mlx5_core] ? sysvec_apic_timer_interrupt+0xb/0x90 mlx5e_handle_rx_dim+0x92/0xd0 [mlx5_core] mlx5e_napi_poll+0x2cd/0xac0 [mlx5_core] ? mlx5e_poll_ico_cq+0xe5/0x6f0 [mlx5_core] busy_poll_stop+0xa2/0x200 ? mlx5e_napi_poll+0x1d9/0xac0 [mlx5_core] ? mlx5e_trigger_irq+0x130/0x130 [mlx5_core] __napi_busy_loop+0x345/0x3b0 ? sysvec_call_function_single+0xb/0x90 ? asm_sysvec_call_function_single+0x16/0x20 ? sysvec_apic_timer_interrupt+0xb/0x90 ? pcpu_free_area+0x1e4/0x2e0 napi_busy_loop+0x11/0x20 xsk_recvmsg+0x10c/0x130 sock_recvmsg+0x44/0x70 __sys_recvfrom+0xbc/0x130 ? __schedule+0x398/0x890 __x64_sys_recvfrom+0x20/0x30 do_syscall_64+0x4c/0x100 entry_SYSCALL_64_after_hwframe+0x4b/0x53 ... Reviewed-by: Cosmin Ratiu Reviewed-by: Jacob Keller ---[ end trace 0000000000000000 ]--- ... ---[ end Kernel panic - not syncing: Fatal exception in interrupt ]--- Fixes: 445a25f6e1a2 ("net/mlx5e: Support updating coalescing configuration = without resetting channels") Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_dim.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_dim.c b/drivers/net= /ethernet/mellanox/mlx5/core/en_dim.c index 298bb74ec5e9..d1d629697e28 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_dim.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_dim.c @@ -113,7 +113,7 @@ int mlx5e_dim_rx_change(struct mlx5e_rq *rq, bool enabl= e) __set_bit(MLX5E_RQ_STATE_DIM, &rq->state); } else { __clear_bit(MLX5E_RQ_STATE_DIM, &rq->state); - + synchronize_net(); mlx5e_dim_disable(rq->dim); rq->dim =3D NULL; } @@ -140,7 +140,7 @@ int mlx5e_dim_tx_change(struct mlx5e_txqsq *sq, bool en= able) __set_bit(MLX5E_SQ_STATE_DIM, &sq->state); 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Miller" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Saeed Mahameed , "Tariq Toukan" , Mark Bloch , , , , Jianbo Liu Subject: [PATCH net 3/3] net/mlx5e: Add new prio for promiscuous mode Date: Thu, 10 Jul 2025 16:53:44 +0300 Message-ID: <1752155624-24095-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752155624-24095-1-git-send-email-tariqt@nvidia.com> References: <1752155624-24095-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468B:EE_|PH7PR12MB5619:EE_ X-MS-Office365-Filtering-Correlation-Id: a436af32-0177-446b-f75f-08ddbfb95c88 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?hjVlS2XIE0SHo5+qq6p4BtYKDB/YSltz+dKwSa7wdZ7TqfL/LfWF/eTYWRrm?= =?us-ascii?Q?MX4GL7VYbwvJvqrS7MnbqNNlZq8XsU0GrttjraDKuQ0U8hLppZ92ZGl5GveB?= =?us-ascii?Q?XuTamry0GjS3AR75i4IN3jTIJrrvYe2RT832//r9mNyDalfRWsjAcElwOtlj?= =?us-ascii?Q?wHjhuW1+5KW7UmYb+1qu7qCtuuQEvHzH2tyVmi0fNkXHkiO02T2jQbQuaVZ/?= =?us-ascii?Q?EtE7gLAWsH7RrQTUaoVllN5ZL5GxkPoG/cUqjw4XNP0M7K7aSTsAVxjhASAF?= =?us-ascii?Q?6905b6EihKcIIYqOiX/52CGxGADEaJ4FzPpB3h0T1kJ8+6weutx9m2j/PsYS?= =?us-ascii?Q?VZdP3VixkeA5VTKV8aYfUYRN22I/qKLqJiEiSZw9w1imqJXcNZ7ZSaQAVpdp?= =?us-ascii?Q?gTXQoWG8WWGruFeXMYlwFiYwJbh/RCET3pLbussaujR60dBfHEQlpjnc0czg?= =?us-ascii?Q?UAWnmChc5DxUOp6i9knfGlMf9BYpmhBcwti4QR/fmP8Mw5F5zJdFtlxoPOlR?= =?us-ascii?Q?aGe8SUADl2uXZFKCLgWU8SiLjoQ/hxng/tH6oFYneifYDAU0R+7awHLyW0N0?= =?us-ascii?Q?+f4lJsV2wv1iAC2qrhk3F6hsFdpV5SW+l9Se1efVc/dNoKRmtoMbHzCB7WnH?= =?us-ascii?Q?2rwBeJmoWbjeKZ5Ae1iRxeNYBUdJ7CPRkhPfRHKp81cQhbrFyqNcnVp9WPIU?= =?us-ascii?Q?5LRdmvHT5LAmnSe81+mQnkS4MN3rw0w84RXbAUfExTRGmfGJfUF6Ft0ePbzl?= =?us-ascii?Q?qK8L/ZLTHfbREUfsp029lEv//AYb3MZ8XZLBtuAs6XU52xVS3f8f+gic0/lk?= =?us-ascii?Q?d1HJm4e9j7VGtghrY/5ejT+gUe/TqDNf2WWt9DwJYVtHnCGR03nl4c9790zY?= =?us-ascii?Q?cnBH1wtMntpSZ0oHbsA8LOwQbKrdWES9jYHcJrexZ2COAG/8SRHicTgVsa8o?= =?us-ascii?Q?1BbCwXY1fv9K3Usz1JUjNlNlCwU0jQKZN0CChC+wOpQ/o7Rn5tXeFfayL74U?= =?us-ascii?Q?BepVCqh5sWdZ4GJ3PkqOQd8qStcH2uIAofNnmxkIff0EwYqqYy6zwa4eCAd9?= =?us-ascii?Q?q84YFsUpNE6CMRxIMNk6w2nfQu0tBSb5AIsPvAXDyeWJwVNki7REcWvikVeD?= =?us-ascii?Q?p0scdY0vQ7tD5GZhLC0eHEM+tH9dVpih2SMtuX0jtOSVKQZSDYkv/4mTNa6j?= =?us-ascii?Q?LwcMqoKlLbFowHg5+NgU1bJXnvsj5+ybAB3y1i0697b0nGCPz1DIHX+GcNt7?= =?us-ascii?Q?ar3FIIFBX3IqdM77VprpXJnOdVFCunjWKigPXUAucJIO6v03GUHf+qlUqfco?= =?us-ascii?Q?S6nZQfh+DbX4H9JSzDZPfERv+pxVb606bjaP3CTYgM3Ap0lwVauPBf1wpt1k?= =?us-ascii?Q?8MO5V8eqDylEcpEnJttaCZ2Rk5xVW05I3s6intBNhvY3b9ytC4JUHBbTT96Q?= =?us-ascii?Q?NhM/15+Fvq9GK4H1OfYdQG7Au3aZfcvyEH+bxCg8z4y0zENs/9KZpJcIi5D6?= =?us-ascii?Q?bRDfmWRINzqF4TkPtHgLZawDj9n/FWAFbB/x?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(7416014)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 13:54:59.7026 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a436af32-0177-446b-f75f-08ddbfb95c88 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5619 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jianbo Liu An optimization for promiscuous mode adds a high-priority steering table with a single catch-all rule to steer all traffic directly to the TTC table. However, a gap exists between the creation of this table and the insertion of the catch-all rule. Packets arriving in this brief window would miss as no rule was inserted yet, unnecessarily incrementing the 'rx_steer_missed_packets' counter and dropped. This patch resolves the issue by introducing a new prio for this table, placing it between MLX5E_TC_PRIO and MLX5E_NIC_PRIO. By doing so, packets arriving during the window now fall through to the next prio (at MLX5E_NIC_PRIO) instead of being dropped. Fixes: 1c46d7409f30 ("net/mlx5e: Optimize promiscuous mode") Signed-off-by: Jianbo Liu Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/fs.h | 9 +++++++-- drivers/net/ethernet/mellanox/mlx5/core/en_fs.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 13 +++++++++---- 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/fs.h b/drivers/net/= ethernet/mellanox/mlx5/core/en/fs.h index b5c3a2a9d2a5..9560fcba643f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/fs.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/fs.h @@ -18,7 +18,8 @@ enum { =20 enum { MLX5E_TC_PRIO =3D 0, - MLX5E_NIC_PRIO + MLX5E_PROMISC_PRIO, + MLX5E_NIC_PRIO, }; =20 struct mlx5e_flow_table { @@ -68,9 +69,13 @@ struct mlx5e_l2_table { MLX5_HASH_FIELD_SEL_DST_IP |\ MLX5_HASH_FIELD_SEL_IPSEC_SPI) =20 -/* NIC prio FTS */ +/* NIC promisc FT level */ enum { MLX5E_PROMISC_FT_LEVEL, +}; + +/* NIC prio FTS */ +enum { MLX5E_VLAN_FT_LEVEL, MLX5E_L2_FT_LEVEL, MLX5E_TTC_FT_LEVEL, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_fs.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_fs.c index 04a969128161..265c4ca85f7d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_fs.c @@ -780,7 +780,7 @@ static int mlx5e_create_promisc_table(struct mlx5e_flow= _steering *fs) ft_attr.max_fte =3D MLX5E_PROMISC_TABLE_SIZE; ft_attr.autogroup.max_num_groups =3D 1; ft_attr.level =3D MLX5E_PROMISC_FT_LEVEL; - ft_attr.prio =3D MLX5E_NIC_PRIO; + ft_attr.prio =3D MLX5E_PROMISC_PRIO; =20 ft->t =3D mlx5_create_auto_grouped_flow_table(fs->ns, &ft_attr); if (IS_ERR(ft->t)) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.c index a8046200d376..3dd9a6f40709 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -113,13 +113,16 @@ #define ETHTOOL_PRIO_NUM_LEVELS 1 #define ETHTOOL_NUM_PRIOS 11 #define ETHTOOL_MIN_LEVEL (KERNEL_MIN_LEVEL + ETHTOOL_NUM_PRIOS) -/* Promiscuous, Vlan, mac, ttc, inner ttc, {UDP/ANY/aRFS/accel/{esp, esp_e= rr}}, IPsec policy, +/* Vlan, mac, ttc, inner ttc, {UDP/ANY/aRFS/accel/{esp, esp_err}}, IPsec p= olicy, * {IPsec RoCE MPV,Alias table},IPsec RoCE policy */ -#define KERNEL_NIC_PRIO_NUM_LEVELS 11 +#define KERNEL_NIC_PRIO_NUM_LEVELS 10 #define KERNEL_NIC_NUM_PRIOS 1 -/* One more level for tc */ -#define KERNEL_MIN_LEVEL (KERNEL_NIC_PRIO_NUM_LEVELS + 1) +/* One more level for tc, and one more for promisc */ +#define KERNEL_MIN_LEVEL (KERNEL_NIC_PRIO_NUM_LEVELS + 2) + +#define KERNEL_NIC_PROMISC_NUM_PRIOS 1 +#define KERNEL_NIC_PROMISC_NUM_LEVELS 1 =20 #define KERNEL_NIC_TC_NUM_PRIOS 1 #define KERNEL_NIC_TC_NUM_LEVELS 3 @@ -187,6 +190,8 @@ static struct init_tree_node { ADD_NS(MLX5_FLOW_TABLE_MISS_ACTION_DEF, ADD_MULTIPLE_PRIO(KERNEL_NIC_TC_NUM_PRIOS, KERNEL_NIC_TC_NUM_LEVELS), + ADD_MULTIPLE_PRIO(KERNEL_NIC_PROMISC_NUM_PRIOS, + KERNEL_NIC_PROMISC_NUM_LEVELS), ADD_MULTIPLE_PRIO(KERNEL_NIC_NUM_PRIOS, KERNEL_NIC_PRIO_NUM_LEVELS))), ADD_PRIO(0, BY_PASS_MIN_LEVEL, 0, FS_CHAINING_CAPS, --=20 2.31.1