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Tue, 8 Jul 2025 14:16:38 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Saeed Mahameed , "Tariq Toukan" , Mark Bloch , , , , Carolina Jubran Subject: [PATCH net-next 1/5] net/mlx5e: Remove unused VLAN insertion logic in TX path Date: Wed, 9 Jul 2025 00:16:23 +0300 Message-ID: <1752009387-13300-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1752009387-13300-1-git-send-email-tariqt@nvidia.com> References: <1752009387-13300-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B5:EE_|SJ0PR12MB6807:EE_ X-MS-Office365-Filtering-Correlation-Id: a05d9993-bd63-48ef-10b6-08ddbe64c52e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?GKyVyruuOwClxdqelatpbXVHhgd41pKaqAU2Yh4zQ7WQgUXdIXvFbyF5xOqi?= =?us-ascii?Q?9At7LL6bVhSt4KOW0nA4KkqDHGTJ6I28Htjqk5gYUwk2HwmC5tLXL2Y8Qn9C?= =?us-ascii?Q?kas74xTwIHvxtDqv3l1qJaUAtQSATWXgthPi+jbCzWZKuV5KcYzG68X7XKN/?= =?us-ascii?Q?EVua6t0GPxlmW2l2NcPE9Ri2Gq/i0j/srhwcMpOcpgQMnX6u3qhnYZ0APuIz?= =?us-ascii?Q?qmr8GzyyIiFD5rLevbdJJNQBGcgQNjrr3u4aUMHk1kPCkRxPTInRYgdIW0da?= =?us-ascii?Q?R/2Y81uGZqOMH/p6ji45dEUtwkJMnGi/BmQwafPVVPe4+KzalnWpsByn9WOO?= =?us-ascii?Q?RxqpejujtXmHYh91Us5tPwjTm9C4SnpgdDDyyZ79/XP6GNKySDGf8TLrDvTT?= =?us-ascii?Q?qSljaYleP8fyyjFahA7PnK7vjcWpnFVIa1tl6scUq+b6uoqKuyGZNx/L1p9Y?= =?us-ascii?Q?SbryxvfIcIJHanbFBYKMLQDpG1WgXC44i86qWqaa79CeSoesIHAaRSzcqSiI?= =?us-ascii?Q?zxw2KOz4P99BAgAUaNk5SztjydmWq957LvKE8gsMLfRnT8QgxPA4HvHi/chF?= =?us-ascii?Q?8HIB3UWgpbytHlOW9m+e3bNTQhy3ayv/OKCWhVmzbh6cCBSJaWMxzJM9aEWc?= =?us-ascii?Q?GkLRLC/pCDVkG7/hlbIUmICjpe5UnncYtLkq9bmU6bQZXOVKBgWSFjy2E90e?= =?us-ascii?Q?KAPELj9K1by/g+HK+RNMUa0EOpvKnyHt6aIOSAG4mQGTwhYifGW4CI4bPxTo?= =?us-ascii?Q?3m08laH5PQDw2HvcuqK4PpR/7i7Jcav1JvUwFhwd88S57uyyJdXYkbYFoeYU?= =?us-ascii?Q?lFls7smi0ie1v+HS2ATo+KxGH0/Wz2xfkhKdVCi6Ba05BzaA4T6mGSLexQEw?= =?us-ascii?Q?k7iKkTmB9tstKSbnf00bT8c5VbfiXPa+rEKTeAO8mi+uNFJG3aerAvnSXLeC?= =?us-ascii?Q?waBRMgrzjc7aBk3zZS7KoQh6rIaxrpPfGIUV+HYCKrwCTL+Fua6mq/AarPpV?= =?us-ascii?Q?9GKqz03bzrO2bLfoX1h8nvp9BR0DiOBSBt/RRHB/8a1WWkIaHW+ckbHaLmhf?= =?us-ascii?Q?u7IRX/0rqOGUzNppVWpkrZx5hU+E9btYQhPKEWV1/DbP2ph5Y7vJPnd9yvIx?= =?us-ascii?Q?zX0039z/gZL+Xa6K7pNrZZ3WJscg6ZuuVs60D4WL50qSq0U/tHHO47TfupEy?= =?us-ascii?Q?A8MoSQ0Sx4bgeykCs/c8kMStBxX6Ai5XalQGPUboFf4jbB/omz5y2uy+KFQL?= =?us-ascii?Q?DJah2KmxpfkenMGoXPN51J7m5djCvkcSeQ3oPsHGIJQAC1N0g6BKSTjhetr9?= =?us-ascii?Q?JCpgZHMViMH/sHACapaDl0kq16FeksAAdfm7VEkr4OwEuIK+gOH6oO5L4Rqi?= =?us-ascii?Q?qe+R6cbNtSaUpGoz5K0VLszsaxwzd+DB0dvuX4MJCf1PmoFsiCuKQC9oiLzl?= =?us-ascii?Q?27wsorqnpT5rM0J+ql4HInuyjVO9zyZWWBmUJnGwjlbQjC4ZbL3f673uPJuI?= =?us-ascii?Q?zBN8bt/RLGPqBqH/vM+wcFPxeA7mee6UKu5A?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2025 21:16:56.9150 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a05d9993-bd63-48ef-10b6-08ddbe64c52e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6807 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran The VLAN insertion capability (`wqe_vlan_insert`) was never enabled on all mlx5 devices. When VLAN TX offload is advertised but this capability is not supported, the driver uses inline headers to insert the VLAN tag. To support this, the driver used to set the `MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE` bit to enforce L2 inline mode when `wqe_vlan_insert` was not supported. Since the capability is disabled on all devices, this logic was always active, and the SQ flag has become redundant. L2 inline is enforced unconditionally for VLAN-tagged packets. The `skb_vlan_tag_present()` check in the else-if block of `mlx5e_sq_xmit_wqe()` is never true by this point in the TX flow, as the VLAN tag has already been inserted by the driver using inline headers. As a result, this code is never executed. Remove the redundant SQ state, dead VLAN insertion code block, and related logic. Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 - drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c | 2 -- drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c | 1 - drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 2 -- drivers/net/ethernet/mellanox/mlx5/core/en_tx.c | 9 +-------- 5 files changed, 1 insertion(+), 14 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 65a73913b9a2..64e69e616b1f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -383,7 +383,6 @@ enum { MLX5E_SQ_STATE_RECOVERING, MLX5E_SQ_STATE_IPSEC, MLX5E_SQ_STATE_DIM, - MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, MLX5E_SQ_STATE_PENDING_XSK_TX, MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, MLX5E_NUM_SQ_STATES, /* Must be kept last */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/ptp.c index 5d0014129a7e..391b4e9c9dc4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c @@ -340,8 +340,6 @@ static int mlx5e_ptp_alloc_txqsq(struct mlx5e_ptp *c, i= nt txq_ix, sq->stats =3D &c->priv->ptp_stats.sq[tc]; sq->ptpsq =3D ptpsq; INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work); - if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert)) - set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state); sq->stop_room =3D param->stop_room; sq->ptp_cyc2time =3D mlx5_sq_ts_translator(mdev); =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c b/dri= vers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c index c3bda4612fa9..bd96988e102c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c @@ -13,7 +13,6 @@ static const char * const sq_sw_state_type_name[] =3D { [MLX5E_SQ_STATE_RECOVERING] =3D "recovering", [MLX5E_SQ_STATE_IPSEC] =3D "ipsec", [MLX5E_SQ_STATE_DIM] =3D "dim", - [MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE] =3D "vlan_need_l2_inline", [MLX5E_SQ_STATE_PENDING_XSK_TX] =3D "pending_xsk_tx", [MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC] =3D "pending_tls_rx_resync", }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index e8e5b347f9b2..fee323ade522 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -1677,8 +1677,6 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, sq->hw_mtu =3D MLX5E_SW2HW_MTU(params, params->sw_mtu); sq->max_sq_mpw_wqebbs =3D mlx5e_get_max_sq_aligned_wqebbs(mdev); INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work); - if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert)) - set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state); if (mlx5_ipsec_device_caps(c->priv->mdev)) set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); if (param->is_mpw) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_tx.c index 55a8629f0792..e6a301ba3254 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c @@ -256,8 +256,7 @@ mlx5e_tx_wqe_inline_mode(struct mlx5e_txqsq *sq, struct= sk_buff *skb, =20 mode =3D sq->min_inline_mode; =20 - if (skb_vlan_tag_present(skb) && - test_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state)) + if (skb_vlan_tag_present(skb)) mode =3D max_t(u8, MLX5_INLINE_MODE_L2, mode); =20 return mode; @@ -483,12 +482,6 @@ mlx5e_sq_xmit_wqe(struct mlx5e_txqsq *sq, struct sk_bu= ff *skb, } eseg->inline_hdr.sz |=3D cpu_to_be16(ihs); dseg +=3D wqe_attr->ds_cnt_inl; - } else if (skb_vlan_tag_present(skb)) { - eseg->insert.type =3D cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN); - if (skb->vlan_proto =3D=3D cpu_to_be16(ETH_P_8021AD)) - eseg->insert.type |=3D cpu_to_be16(MLX5_ETH_WQE_SVLAN); - eseg->insert.vlan_tci =3D cpu_to_be16(skb_vlan_tag_get(skb)); - stats->added_vlan_packets++; } =20 dseg +=3D wqe_attr->ds_cnt_ids; --=20 2.31.1