From nobody Tue Oct 7 16:00:33 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D3D32EAB92 for ; Tue, 8 Jul 2025 18:20:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751998845; cv=none; b=LV3drwids43xnFBCJwkeRM6YEi7gJrmbc/ULwVCBV2MSZsNmIr+BiqAaWX/5fBIPFWfzyOBuSGlAJ/CwiSdpMw8UYzaQvfSm2b16rZz8c1cBheN9NDwnt4TaL3D+9PSse0gYE6p7e8S7DGKtdv+3g2EQau1oOx3HcR2VLEtdCt4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751998845; c=relaxed/simple; bh=rVxqH4RN16NZK2teeLlgW67Jyd1mg5tiUUiXcX3tXm0=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=SCj1DuC2kVMuq3xhPMSGyqje8NuHtb9rdA66qLh3NjrGeolM15CRFUZb9ad38W5FaVUSZVEh9wcr6KnrUgq/OEsyN9ZK+hL7XCzfhTKAsYEXcJwsH4XpLe+S7vct+YBzFhPW18O2+DSoBHI3j+eeLtfO84BU69SEDhqNE3um838= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=VmsshhMf; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=+nanXxUe; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="VmsshhMf"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="+nanXxUe" Date: Tue, 08 Jul 2025 18:20:41 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1751998842; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PJEWgPJxU5b0WvB+okOsOgRCfq0+v1zGl1uYdN4pWJM=; b=VmsshhMf444WYpnY2MBQLoLhtcXvqb/m3WG/+ZOfcoO/MMRmajMz5kGGWAA/Kx/rG8VXmL eh0mOnTkeYXP//fTnIhUyXqfKJNl5OIAA5eDm+NvHiyBvAYZ65oqscq0c2ychaMXfi01CO g7jIvfE9gx4GA9fuaaxvuC7Tti/Cp8oFjTEsGS4dN4i0MhpkXHeyX08SXVII4oCRnclNyT 4Td2j1n0DTy5MIuo9zOM2uIPaMtCXGRS/sB4lrRYUgcdTJ0k8XSjXA3471uIX+kxTe6U0G 2FkdgpywXjkEEdvbp4GfinVQcmZU6mFlcgijyVI9TqbHbsxVP8jIbF28caXrmQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1751998842; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PJEWgPJxU5b0WvB+okOsOgRCfq0+v1zGl1uYdN4pWJM=; b=+nanXxUe3t1y7/IJbBIvCAws1744fL3cnll1kqP90OSwERzh9O/OucxkJqP+0y0Uacjl63 SSRzPFiNmqjCV9Bg== From: "irqchip-bot for Lorenzo Pieralisi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] arm64/sysreg: Add ICC_PPI_HMR_EL1 Cc: Lorenzo Pieralisi , Jonathan Cameron , Marc Zyngier , Will Deacon , Catalin Marinas , tglx@linutronix.de In-Reply-To: <20250703-gicv5-host-v7-5-12e71f1b3528@kernel.org> References: <20250703-gicv5-host-v7-5-12e71f1b3528@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <175199884187.406.11968839936504399891.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 4ee38cd9af9dd72ee26645e90eb26b6251ba9acb Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/4ee38cd9af9dd72ee26645e90eb26b6251ba9acb Author: Lorenzo Pieralisi AuthorDate: Thu, 03 Jul 2025 12:24:55 +02:00 Committer: Marc Zyngier CommitterDate: Tue, 08 Jul 2025 18:35:50 +01:00 arm64/sysreg: Add ICC_PPI_HMR_EL1 Add ICC_PPI_HMR_EL1 registers sysreg description. Signed-off-by: Lorenzo Pieralisi Reviewed-by: Jonathan Cameron Reviewed-by: Marc Zyngier Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier Acked-by: Catalin Marinas Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-5-12e71f1b3528@kerne= l.org Signed-off-by: Marc Zyngier --- arch/arm64/tools/sysreg | 75 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 75 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 81b32f5..7f096ef 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3024,6 +3024,81 @@ Sysreg PMIAR_EL1 3 0 9 14 7 Field 63:0 ADDRESS EndSysreg =20 +SysregFields ICC_PPI_HMRx_EL1 +Field 63 HM63 +Field 62 HM62 +Field 61 HM61 +Field 60 HM60 +Field 59 HM59 +Field 58 HM58 +Field 57 HM57 +Field 56 HM56 +Field 55 HM55 +Field 54 HM54 +Field 53 HM53 +Field 52 HM52 +Field 51 HM51 +Field 50 HM50 +Field 49 HM49 +Field 48 HM48 +Field 47 HM47 +Field 46 HM46 +Field 45 HM45 +Field 44 HM44 +Field 43 HM43 +Field 42 HM42 +Field 41 HM41 +Field 40 HM40 +Field 39 HM39 +Field 38 HM38 +Field 37 HM37 +Field 36 HM36 +Field 35 HM35 +Field 34 HM34 +Field 33 HM33 +Field 32 HM32 +Field 31 HM31 +Field 30 HM30 +Field 29 HM29 +Field 28 HM28 +Field 27 HM27 +Field 26 HM26 +Field 25 HM25 +Field 24 HM24 +Field 23 HM23 +Field 22 HM22 +Field 21 HM21 +Field 20 HM20 +Field 19 HM19 +Field 18 HM18 +Field 17 HM17 +Field 16 HM16 +Field 15 HM15 +Field 14 HM14 +Field 13 HM13 +Field 12 HM12 +Field 11 HM11 +Field 10 HM10 +Field 9 HM9 +Field 8 HM8 +Field 7 HM7 +Field 6 HM6 +Field 5 HM5 +Field 4 HM4 +Field 3 HM3 +Field 2 HM2 +Field 1 HM1 +Field 0 HM0 +EndSysregFields + +Sysreg ICC_PPI_HMR0_EL1 3 0 12 10 0 +Fields ICC_PPI_HMRx_EL1 +EndSysreg + +Sysreg ICC_PPI_HMR1_EL1 3 0 12 10 1 +Fields ICC_PPI_HMRx_EL1 +EndSysreg + Sysreg ICC_ICSR_EL1 3 0 12 10 4 Res0 63:48 Field 47:32 IAFFID