From nobody Tue Oct 7 16:03:57 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2753B21CC44 for ; Tue, 8 Jul 2025 18:20:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751998836; cv=none; b=A4RQ9ebOKeiqOgiazYx5TGVhd/KAbbbMtgCij6CDu/Avq8bV5JAxmRu08lmS9JW4Ti3Iu+rtKen8qmEtD1RQxMtuzrSdBFWq12k4JZpmA6tpdjCJ/uXdY5HQmn+YBqR7ctjBTsXsHxdEYNQcbgO6qS0sad4T1GFhH31AFolRj1c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751998836; c=relaxed/simple; bh=w3eU8WULaDLZbPW/zfygCj7wAiTpqHvBg9M9MfqkWVs=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=IcVmp+aH+jqn/mVIDDMzP1lh8EYKFRsa9eNf+sVc6zThJLbTnjSmgY5CPAb97KNNhjbwCmNJCGHz+kxtz1H0l6q1nEMtmL67azIThFjvEtg5IeQaNftzNYCztyR2gkOzL97kE0FRnOK9IvUE6YUbEqYLnv52aOtpHPcjYudfbTs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=iA6Qs896; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Y/+3IRV0; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="iA6Qs896"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Y/+3IRV0" Date: Tue, 08 Jul 2025 18:20:31 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1751998832; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OtasPYvFqkxwfZSnTtb7sIJzmOMwu7TyDZFDiu3kIJw=; b=iA6Qs89667+BcSL3UaBqLZb3g8liKsR/uhzzKYnzP/BmZ4vR+AZQVv22njo/bGMSTY3SCf u1mcZmODVoIpOsXy2ujKj99gspmL8QEUoRgICc+7JEMwrkJEmdhhKHc+VhPbxI0SfSF1Pv W+8NwMfObb02r8ZbriCQ3p8o6CC1FWJINZbGekFL/1IRo5gSfjvT7pbmg/fEkyPDNJdlLZ s/G3J+emw7F9Vj0UxBgL3SNNJZSluCGkJJTrZ0ynn9J4TmwEIbebbaQWLWuxUdmA8Vy86u WcLp8lC5xCl55UMPDFkZjOxh7afHU7Dn/HfzZ5LrBeH3CglDplF2eHKkIYwMXw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1751998832; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OtasPYvFqkxwfZSnTtb7sIJzmOMwu7TyDZFDiu3kIJw=; b=Y/+3IRV0uN1V+bTqCfkJA4KYVyW2mqVzoGjHJDGfBWc+3FNnpeS95TZ+/7IM/tVAUN9uHc CKQanabzj9WcT9AA== From: "irqchip-bot for Lorenzo Pieralisi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability Cc: Lorenzo Pieralisi , Marc Zyngier , Will Deacon , Catalin Marinas , tglx@linutronix.de In-Reply-To: <20250703-gicv5-host-v7-17-12e71f1b3528@kernel.org> References: <20250703-gicv5-host-v7-17-12e71f1b3528@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <175199883123.406.10390811721292732320.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 988699f9e6b61d25a1448f7ff3c4a80b41e9d9e6 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/988699f9e6b61d25a1448f7ff3c4a80b41e9d9e6 Author: Lorenzo Pieralisi AuthorDate: Thu, 03 Jul 2025 12:25:07 +02:00 Committer: Marc Zyngier CommitterDate: Tue, 08 Jul 2025 18:35:51 +01:00 arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability Implement the GCIE capability as a strict boot cpu capability to detect whether architectural GICv5 support is available in HW. Plug it in with a naming consistent with the existing GICv3 CPU interface capability. Signed-off-by: Lorenzo Pieralisi Reviewed-by: Marc Zyngier Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier Acked-by: Catalin Marinas Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-17-12e71f1b3528@kern= el.org Signed-off-by: Marc Zyngier --- arch/arm64/kernel/cpufeature.c | 7 +++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 8 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 42ba76b..2fa2612 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -3061,6 +3061,13 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .matches =3D has_pmuv3, }, #endif + { + .desc =3D "GICv5 CPU interface", + .type =3D ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, + .capability =3D ARM64_HAS_GICV5_CPUIF, + .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) + }, {}, }; =20 diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index a7a4d9e..8665e4c 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -36,6 +36,7 @@ HAS_GENERIC_AUTH_ARCH_QARMA3 HAS_GENERIC_AUTH_ARCH_QARMA5 HAS_GENERIC_AUTH_IMP_DEF HAS_GICV3_CPUIF +HAS_GICV5_CPUIF HAS_GIC_PRIO_MASKING HAS_GIC_PRIO_RELAXED_SYNC HAS_HCR_NV1