From nobody Tue Oct 7 16:00:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C45221ABDB for ; Tue, 8 Jul 2025 18:20:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751998823; cv=none; b=bnEfUuY+o4P0xG4eWXJKzxaxZ/8+fhWASfOQ3+OQflwvk5ias7BSR3CY2H14aEWQKRD8zYU2ayTBq3bLlsfPN1XhgAfJXspTXlF0oFC6gOp11IE22kMbGVai8MOX3z/DeJUIqtJafR+1C4EiPCrwHR7tS38V6Ejtc56VpL5eeDk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751998823; c=relaxed/simple; bh=cMWQFzEsdkOOFhZY+QUs/mPVgEUZjp8mit2HM2hyZw8=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=HweWG3aQA0Cm78Ln8uJPu+Vj8Ji2BxvhI6jjD5ma74DlIgQikcJBwv8uys3JhomAY+3gIVVDTo+WCPb3+5DxwfXfAsjzUNFDVas1TetKHD/QouX3Vl9mGiMqjKSSfN9uBQSjmwAB5/ECE2CwS3CTufRvvo6KxqUtek0vgw5v6g4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=1YWJ8eGD; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hBIJF+x+; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="1YWJ8eGD"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hBIJF+x+" Date: Tue, 08 Jul 2025 18:20:18 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1751998819; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=M//KeqEkHWBzX23FavFcLoyWNQijQqTMq34dBrdSlP8=; b=1YWJ8eGD0/P4fhDfowUBrs3WdiveEfwqFNT8IzXLJXTv35b8fuSdiox43QWa0PZJqTlTse w4QDakTUHRwBd4zL+w1CL00IImimPklEbnM1V97oU/YyXitHosFZr3htrP//8tJna/Q5BZ QTz0UsxpkuZWGvaO1oLGgVx8d6bztCn8EapUcMzjJamvrGYO5z9rUrRC7S9WTDEcsWcJju KTOF66n5In/H/wg8EHOpca5gv/AopvXVjAX3b8hd0HEAQ4afRcn6Nu7gFVXW3p6DHWbLmZ Arc9pd6MJXENN+v9VsQGXiqKNAlGL5SqWA6gVn2iYGKAYw29s7TXkySTYLmGPQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1751998819; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=M//KeqEkHWBzX23FavFcLoyWNQijQqTMq34dBrdSlP8=; b=hBIJF+x+2UX6OuFKNNjoz95woQygVGivPaTtCFEOdyTpdPZAjFN9f+iW3BrqQfzxDO0aMg U6Sq88T4d7MTU0BQ== From: "irqchip-bot for Lorenzo Pieralisi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] docs: arm64: gic-v5: Document booting requirements for GICv5 Cc: Lorenzo Pieralisi , Marc Zyngier , Will Deacon , Catalin Marinas , tglx@linutronix.de In-Reply-To: <20250703-gicv5-host-v7-30-12e71f1b3528@kernel.org> References: <20250703-gicv5-host-v7-30-12e71f1b3528@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <175199881878.406.6272189331689783193.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 42d36969e307cf0c7a523755a6f66cecb69cd32c Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/42d36969e307cf0c7a523755a6f66cecb69cd32c Author: Lorenzo Pieralisi AuthorDate: Thu, 03 Jul 2025 12:25:20 +02:00 Committer: Marc Zyngier CommitterDate: Tue, 08 Jul 2025 18:35:52 +01:00 docs: arm64: gic-v5: Document booting requirements for GICv5 Document the requirements for booting a kernel on a system implementing a GICv5 interrupt controller. Specifically, other than DT/ACPI providing the required firmware representation, define what traps must be disabled if the kernel is booted at EL1 on a system where EL2 is implemented. Signed-off-by: Lorenzo Pieralisi Reviewed-by: Marc Zyngier Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier Acked-by: Catalin Marinas Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-30-12e71f1b3528@kern= el.org Signed-off-by: Marc Zyngier --- Documentation/arch/arm64/booting.rst | 41 +++++++++++++++++++++++++++- 1 file changed, 41 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm6= 4/booting.rst index ee9b790..83e0373 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -223,6 +223,47 @@ Before jumping into the kernel, the following conditio= ns must be met: =20 - SCR_EL3.HCE (bit 8) must be initialised to 0b1. =20 + For systems with a GICv5 interrupt controller to be used in v5 mode: + + - If the kernel is entered at EL1 and EL2 is present: + + - ICH_HFGRTR_EL2.ICC_PPI_ACTIVERn_EL1 (bit 20) must be initialised t= o 0b1. + - ICH_HFGRTR_EL2.ICC_PPI_PRIORITYRn_EL1 (bit 19) must be initialised= to 0b1. + - ICH_HFGRTR_EL2.ICC_PPI_PENDRn_EL1 (bit 18) must be initialised to = 0b1. + - ICH_HFGRTR_EL2.ICC_PPI_ENABLERn_EL1 (bit 17) must be initialised t= o 0b1. + - ICH_HFGRTR_EL2.ICC_PPI_HMRn_EL1 (bit 16) must be initialised to 0b= 1. + - ICH_HFGRTR_EL2.ICC_IAFFIDR_EL1 (bit 7) must be initialised to 0b1. + - ICH_HFGRTR_EL2.ICC_ICSR_EL1 (bit 6) must be initialised to 0b1. + - ICH_HFGRTR_EL2.ICC_PCR_EL1 (bit 5) must be initialised to 0b1. + - ICH_HFGRTR_EL2.ICC_HPPIR_EL1 (bit 4) must be initialised to 0b1. + - ICH_HFGRTR_EL2.ICC_HAPR_EL1 (bit 3) must be initialised to 0b1. + - ICH_HFGRTR_EL2.ICC_CR0_EL1 (bit 2) must be initialised to 0b1. + - ICH_HFGRTR_EL2.ICC_IDRn_EL1 (bit 1) must be initialised to 0b1. + - ICH_HFGRTR_EL2.ICC_APR_EL1 (bit 0) must be initialised to 0b1. + + - ICH_HFGWTR_EL2.ICC_PPI_ACTIVERn_EL1 (bit 20) must be initialised t= o 0b1. + - ICH_HFGWTR_EL2.ICC_PPI_PRIORITYRn_EL1 (bit 19) must be initialised= to 0b1. + - ICH_HFGWTR_EL2.ICC_PPI_PENDRn_EL1 (bit 18) must be initialised to = 0b1. + - ICH_HFGWTR_EL2.ICC_PPI_ENABLERn_EL1 (bit 17) must be initialised t= o 0b1. + - ICH_HFGWTR_EL2.ICC_ICSR_EL1 (bit 6) must be initialised to 0b1. + - ICH_HFGWTR_EL2.ICC_PCR_EL1 (bit 5) must be initialised to 0b1. + - ICH_HFGWTR_EL2.ICC_CR0_EL1 (bit 2) must be initialised to 0b1. + - ICH_HFGWTR_EL2.ICC_APR_EL1 (bit 0) must be initialised to 0b1. + + - ICH_HFGITR_EL2.GICRCDNMIA (bit 10) must be initialised to 0b1. + - ICH_HFGITR_EL2.GICRCDIA (bit 9) must be initialised to 0b1. + - ICH_HFGITR_EL2.GICCDDI (bit 8) must be initialised to 0b1. + - ICH_HFGITR_EL2.GICCDEOI (bit 7) must be initialised to 0b1. + - ICH_HFGITR_EL2.GICCDHM (bit 6) must be initialised to 0b1. + - ICH_HFGITR_EL2.GICCDRCFG (bit 5) must be initialised to 0b1. + - ICH_HFGITR_EL2.GICCDPEND (bit 4) must be initialised to 0b1. + - ICH_HFGITR_EL2.GICCDAFF (bit 3) must be initialised to 0b1. + - ICH_HFGITR_EL2.GICCDPRI (bit 2) must be initialised to 0b1. + - ICH_HFGITR_EL2.GICCDDIS (bit 1) must be initialised to 0b1. + - ICH_HFGITR_EL2.GICCDEN (bit 0) must be initialised to 0b1. + + - The DT or ACPI tables must describe a GICv5 interrupt controller. + For systems with a GICv3 interrupt controller to be used in v3 mode: - If EL3 is present: