From nobody Wed Oct 8 20:01:06 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C49CA26B751; Tue, 24 Jun 2025 23:31:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750807863; cv=none; b=L1NK/5xSnfhOxJEaISulV/uyqlH8U+lgD0CNRnMTLehuiNIM1Q3YeGjKvwnvQYOIPcCF7ZwSEy8qgchejXiA3qGlbZ4dXf+B58lbV+U66dUMqCtADv2hfdcdClauW9ME025mm7p4j+h01SR6lCHRogw3vPQKKWGjodwwJ7C3gng= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750807863; c=relaxed/simple; bh=YbCLBhJbUdelYgjzLt2DRQl3g12Bx1eD4ZsmUclcup4=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=K1nzNTL5cCkINj6d4Gx7bDDznZNVWm/Yxv9wZmB5z/7mHgEbPkDnSo2eCwab8Vt5t/ORA0UXRAHxgRHMtpWg/3Q13RWdcNhidMs2u8tdpGMAX19C6NoMS0ywCLvNVAjHhS5KedUuh8ygWq5itpCJzsWbxIK3Vb8VtTSzwVvaVNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0x4YasJL; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=JcOh2441; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0x4YasJL"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="JcOh2441" Date: Tue, 24 Jun 2025 23:30:58 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1750807859; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=PFi57pI7SXW7krG0eFr4/5IQ5Y0pzBy9MzPi5Gy+ygM=; b=0x4YasJLozOjioftIKf2ugWIyqJ5axIgD7/G4SaqhQt2j9SZFDk1OcT0scsYbQVfbgKkwH YSos3Hb5PxheEHWMFghlaeEnJBqC37SlHHSzVlIlDxM01hMLOQY0MhX2t50fbOh94ttEHR JLZ+BYTOfPeYKDfYhNPgEouhismJmvUcgitYx4q+qoG7rY5GctrCZiQdzS4sEEta2Ip66f CJKNNBZOvbUKV/SzAJD13J+Z1fExPXBDoAOjsqJLDjUgWj4//I1Hj2DyhNuy+OdYA2/9oO E+zkRuhreSilWWTpqgW1vuYAV1eyRPHuiSksNyiM3MXdcgugcS7thfIyoxfG1w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1750807859; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=PFi57pI7SXW7krG0eFr4/5IQ5Y0pzBy9MzPi5Gy+ygM=; b=JcOh2441pgeYemkN5qqpPg4db5+qwRQHYLigAjiTMcL/dyX0uMu4z0uhLVfls4N3jV0Snw MXDOnPKT+phSIHDA== From: "tip-bot2 for Chao Gao" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/fpu] x86/fpu: Initialize guest fpstate and FPU pseudo container from guest defaults Cc: "Chang S. Bae" , Chao Gao , Dave Hansen , Rick Edgecombe , John Allen , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <175080785887.406.10961378813772629174.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/fpu branch of tip: Commit-ID: 509e880b779592aafb41b3b23de3df7e4e2e2fcf Gitweb: https://git.kernel.org/tip/509e880b779592aafb41b3b23de3df7e4= e2e2fcf Author: Chao Gao AuthorDate: Thu, 22 May 2025 08:10:06 -07:00 Committer: Dave Hansen CommitterDate: Tue, 24 Jun 2025 13:46:32 -07:00 x86/fpu: Initialize guest fpstate and FPU pseudo container from guest defau= lts fpu_alloc_guest_fpstate() currently uses host defaults to initialize guest fpstate and pseudo containers. Guest defaults were introduced to differentiate the features and sizes of host and guest FPUs. Switch to using guest defaults instead. Adjust __fpstate_reset() to handle different defaults for host and guest FPUs. And to distinguish between the types of FPUs, move the initialization of indicators (is_guest and is_valloc) before the reset. Suggested-by: Chang S. Bae Signed-off-by: Chao Gao Signed-off-by: Dave Hansen Reviewed-by: Rick Edgecombe Reviewed-by: John Allen Link: https://lore.kernel.org/all/20250522151031.426788-4-chao.gao%40intel.= com --- arch/x86/kernel/fpu/core.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 94706a5..e027051 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -243,19 +243,22 @@ bool fpu_alloc_guest_fpstate(struct fpu_guest *gfpu) struct fpstate *fpstate; unsigned int size; =20 - size =3D fpu_kernel_cfg.default_size + ALIGN(offsetof(struct fpstate, reg= s), 64); + size =3D guest_default_cfg.size + ALIGN(offsetof(struct fpstate, regs), 6= 4); + fpstate =3D vzalloc(size); if (!fpstate) return false; =20 + /* Initialize indicators to reflect properties of the fpstate */ + fpstate->is_valloc =3D true; + fpstate->is_guest =3D true; + /* Leave xfd to 0 (the reset value defined by spec) */ __fpstate_reset(fpstate, 0); fpstate_init_user(fpstate); - fpstate->is_valloc =3D true; - fpstate->is_guest =3D true; =20 gfpu->fpstate =3D fpstate; - gfpu->xfeatures =3D fpu_kernel_cfg.default_features; + gfpu->xfeatures =3D guest_default_cfg.features; =20 /* * KVM sets the FP+SSE bits in the XSAVE header when copying FPU state @@ -544,10 +547,22 @@ void fpstate_init_user(struct fpstate *fpstate) =20 static void __fpstate_reset(struct fpstate *fpstate, u64 xfd) { - /* Initialize sizes and feature masks */ - fpstate->size =3D fpu_kernel_cfg.default_size; + /* + * Supervisor features (and thus sizes) may diverge between guest + * FPUs and host FPUs, as some supervisor features are supported + * for guests despite not being utilized by the host. User + * features and sizes are always identical, which allows for + * common guest and userspace ABI. + */ + if (fpstate->is_guest) { + fpstate->size =3D guest_default_cfg.size; + fpstate->xfeatures =3D guest_default_cfg.features; + } else { + fpstate->size =3D fpu_kernel_cfg.default_size; + fpstate->xfeatures =3D fpu_kernel_cfg.default_features; + } + fpstate->user_size =3D fpu_user_cfg.default_size; - fpstate->xfeatures =3D fpu_kernel_cfg.default_features; fpstate->user_xfeatures =3D fpu_user_cfg.default_features; fpstate->xfd =3D xfd; }