From nobody Sat Oct 11 08:29:21 2025 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2A6262E6108; Wed, 11 Jun 2025 14:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749651077; cv=none; b=u0ncPxwTxcY96FAJxKZj8xkn+3cQX8+kkeF99mdYcXn3ALOBoOYuM8/SbLpNtsofq8Dvej4T494LVMDZU2mFvac9ibLtTU2kl+VFREpKZG1EdMLqrPLBI+ztA/i9aTXJE1wISk8Wy4dpvav/0ye5nRLZqGE7zmJygVcSyg52EWY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749651077; c=relaxed/simple; bh=R0qI1l+Dp+BQxaI9jUomP00rTdQeSJOMBr9UWWJTbf8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Z6+b8YEbMZMy+ofNIF+N5vOZw2kBr64lY9yj8G+SoN4ADhsqN6ZdInPGkPyCSr8EtkLEUXBne0dXlqtNsiu7rhUUTzfg6uZCKVvNRcIurbbCQ9zTUclfBJa9koTXd3F0i4NWIA6eojyTH6ug7h1dzC0YZvhcOHzpEWWIF21VGEo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com; spf=pass smtp.mailfrom=linux.microsoft.com; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b=HKLF/gTR; arc=none smtp.client-ip=13.77.154.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="HKLF/gTR" Received: by linux.microsoft.com (Postfix, from userid 1134) id D3AB4203EE0A; Wed, 11 Jun 2025 07:11:14 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com D3AB4203EE0A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1749651074; bh=7Vj/WeKE7E1u91ZSnRU675QpCJSIZVJHWMl588pdaUs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HKLF/gTRvi3pyM9c1bdYHW9fLq1zCt4EIES4UrtrEKQiWEMf4OHM5VxxRWDnW6dJr Tcyn0DMtVq+6ihsMOKyLQvG1xwiee46sxIW3lFj/VOHAorFM/sETZxcdi0I79tjejM fEkafs7OMlUnXDMm92xc1KRW0eLH8tXWX3ZIBMJE= From: Shradha Gupta To: Dexuan Cui , Wei Liu , Haiyang Zhang , "K. Y. Srinivasan" , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Konstantin Taranov , Simon Horman , Leon Romanovsky , Maxim Levitsky , Erni Sri Satya Vennela , Peter Zijlstra , Michael Kelley Cc: Shradha Gupta , linux-hyperv@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Nipun Gupta , Yury Norov , Jason Gunthorpe , Jonathan Cameron , Anna-Maria Behnsen , Kevin Tian , Long Li , Thomas Gleixner , Bjorn Helgaas , Rob Herring , Manivannan Sadhasivam , =?UTF-8?q?Krzysztof=20Wilczy=EF=BF=BD=7EDski?= , Lorenzo Pieralisi , netdev@vger.kernel.org, linux-rdma@vger.kernel.org, Paul Rosswurm , Shradha Gupta Subject: [PATCH v6 5/5] net: mana: Allocate MSI-X vectors dynamically Date: Wed, 11 Jun 2025 07:11:13 -0700 Message-Id: <1749651073-10399-1-git-send-email-shradhagupta@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1749650984-9193-1-git-send-email-shradhagupta@linux.microsoft.com> References: <1749650984-9193-1-git-send-email-shradhagupta@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently, the MANA driver allocates MSI-X vectors statically based on MANA_MAX_NUM_QUEUES and num_online_cpus() values and in some cases ends up allocating more vectors than it needs. This is because, by this time we do not have a HW channel and do not know how many IRQs should be allocated. To avoid this, we allocate 1 MSI-X vector during the creation of HWC and after getting the value supported by hardware, dynamically add the remaining MSI-X vectors. Signed-off-by: Shradha Gupta Reviewed-by: Haiyang Zhang --- Changes in v5: * Correctly initialized start_irqs, so that it is cleaned properly * rearranged the cpu_lock to minimize the critical section --- Changes in v4: * added BUG_ON at appropriate places * moved xa_destroy to mana_gd_remove() * rearragned the cleanup logic in mana_gd_setup_dyn_irqs() * simplified processing around start_irq_index in mana_gd_setup_irqs() * return 0 instead of return err as appropriate --- Changes in v3: * implemented irq_contexts as xarrays rather than list * split the patch to create a perparation patch around irq_setup() * add log when IRQ allocation/setup for remaining IRQs fails --- Changes in v2: * Use string 'MSI-X vectors' instead of 'pci vectors' * make skip-cpu a bool instead of int * rearrange the comment arout skip_cpu variable appropriately * update the capability bit for driver indicating dynamic IRQ * allocation * enforced max line length to 80 * enforced RCT convention * initialized gic to NULL, for when there is a possibility of gic not being populated correctly --- .../net/ethernet/microsoft/mana/gdma_main.c | 311 +++++++++++++----- include/net/mana/gdma.h | 8 +- 2 files changed, 235 insertions(+), 84 deletions(-) diff --git a/drivers/net/ethernet/microsoft/mana/gdma_main.c b/drivers/net/= ethernet/microsoft/mana/gdma_main.c index 6e468c0f2c40..d0040c12b8a2 100644 --- a/drivers/net/ethernet/microsoft/mana/gdma_main.c +++ b/drivers/net/ethernet/microsoft/mana/gdma_main.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include =20 @@ -80,8 +82,15 @@ static int mana_gd_query_max_resources(struct pci_dev *p= dev) return err ? err : -EPROTO; } =20 - if (gc->num_msix_usable > resp.max_msix) - gc->num_msix_usable =3D resp.max_msix; + if (!pci_msix_can_alloc_dyn(pdev)) { + if (gc->num_msix_usable > resp.max_msix) + gc->num_msix_usable =3D resp.max_msix; + } else { + /* If dynamic allocation is enabled we have already allocated + * hwc msi + */ + gc->num_msix_usable =3D min(resp.max_msix, num_online_cpus() + 1); + } =20 if (gc->num_msix_usable <=3D 1) return -ENOSPC; @@ -483,7 +492,9 @@ static int mana_gd_register_irq(struct gdma_queue *queu= e, } =20 queue->eq.msix_index =3D msi_index; - gic =3D &gc->irq_contexts[msi_index]; + gic =3D xa_load(&gc->irq_contexts, msi_index); + if (WARN_ON(!gic)) + return -EINVAL; =20 spin_lock_irqsave(&gic->lock, flags); list_add_rcu(&queue->entry, &gic->eq_list); @@ -508,7 +519,10 @@ static void mana_gd_deregiser_irq(struct gdma_queue *q= ueue) if (WARN_ON(msix_index >=3D gc->num_msix_usable)) return; =20 - gic =3D &gc->irq_contexts[msix_index]; + gic =3D xa_load(&gc->irq_contexts, msix_index); + if (WARN_ON(!gic)) + return; + spin_lock_irqsave(&gic->lock, flags); list_for_each_entry_rcu(eq, &gic->eq_list, entry) { if (queue =3D=3D eq) { @@ -1366,47 +1380,108 @@ static int irq_setup(unsigned int *irqs, unsigned = int len, int node, return 0; } =20 -static int mana_gd_setup_irqs(struct pci_dev *pdev) +static int mana_gd_setup_dyn_irqs(struct pci_dev *pdev, int nvec) { struct gdma_context *gc =3D pci_get_drvdata(pdev); - unsigned int max_queues_per_port; struct gdma_irq_context *gic; - unsigned int max_irqs, cpu; - int start_irq_index =3D 1; - int nvec, *irqs, irq; - int err, i =3D 0, j; + bool skip_first_cpu =3D false; + int *irqs, irq, err, i; =20 - cpus_read_lock(); - max_queues_per_port =3D num_online_cpus(); - if (max_queues_per_port > MANA_MAX_NUM_QUEUES) - max_queues_per_port =3D MANA_MAX_NUM_QUEUES; + irqs =3D kmalloc_array(nvec, sizeof(int), GFP_KERNEL); + if (!irqs) + return -ENOMEM; + + /* + * While processing the next pci irq vector, we start with index 1, + * as IRQ vector at index 0 is already processed for HWC. + * However, the population of irqs array starts with index 0, to be + * further used in irq_setup() + */ + for (i =3D 1; i <=3D nvec; i++) { + gic =3D kzalloc(sizeof(*gic), GFP_KERNEL); + if (!gic) { + err =3D -ENOMEM; + goto free_irq; + } + gic->handler =3D mana_gd_process_eq_events; + INIT_LIST_HEAD(&gic->eq_list); + spin_lock_init(&gic->lock); =20 - /* Need 1 interrupt for the Hardware communication Channel (HWC) */ - max_irqs =3D max_queues_per_port + 1; + snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_q%d@pci:%s", + i - 1, pci_name(pdev)); =20 - nvec =3D pci_alloc_irq_vectors(pdev, 2, max_irqs, PCI_IRQ_MSIX); - if (nvec < 0) { - cpus_read_unlock(); - return nvec; + /* one pci vector is already allocated for HWC */ + irqs[i - 1] =3D pci_irq_vector(pdev, i); + if (irqs[i - 1] < 0) { + err =3D irqs[i - 1]; + goto free_current_gic; + } + + err =3D request_irq(irqs[i - 1], mana_gd_intr, 0, gic->name, gic); + if (err) + goto free_current_gic; + + xa_store(&gc->irq_contexts, i, gic, GFP_KERNEL); } - if (nvec <=3D num_online_cpus()) - start_irq_index =3D 0; =20 - irqs =3D kmalloc_array((nvec - start_irq_index), sizeof(int), GFP_KERNEL); - if (!irqs) { - err =3D -ENOMEM; - goto free_irq_vector; + /* + * When calling irq_setup() for dynamically added IRQs, if number of + * CPUs is more than or equal to allocated MSI-X, we need to skip the + * first CPU sibling group since they are already affinitized to HWC IRQ + */ + cpus_read_lock(); + if (gc->num_msix_usable <=3D num_online_cpus()) + skip_first_cpu =3D true; + + err =3D irq_setup(irqs, nvec, gc->numa_node, skip_first_cpu); + if (err) { + cpus_read_unlock(); + goto free_irq; } =20 - gc->irq_contexts =3D kcalloc(nvec, sizeof(struct gdma_irq_context), - GFP_KERNEL); - if (!gc->irq_contexts) { - err =3D -ENOMEM; - goto free_irq_array; + cpus_read_unlock(); + kfree(irqs); + return 0; + +free_current_gic: + kfree(gic); +free_irq: + for (i -=3D 1; i > 0; i--) { + irq =3D pci_irq_vector(pdev, i); + gic =3D xa_load(&gc->irq_contexts, i); + if (WARN_ON(!gic)) + continue; + + irq_update_affinity_hint(irq, NULL); + free_irq(irq, gic); + xa_erase(&gc->irq_contexts, i); + kfree(gic); } + kfree(irqs); + return err; +} + +static int mana_gd_setup_irqs(struct pci_dev *pdev, int nvec) +{ + struct gdma_context *gc =3D pci_get_drvdata(pdev); + struct gdma_irq_context *gic; + int *irqs, *start_irqs, irq; + unsigned int cpu; + int err, i; + + irqs =3D kmalloc_array(nvec, sizeof(int), GFP_KERNEL); + if (!irqs) + return -ENOMEM; + + start_irqs =3D irqs; =20 for (i =3D 0; i < nvec; i++) { - gic =3D &gc->irq_contexts[i]; + gic =3D kzalloc(sizeof(*gic), GFP_KERNEL); + if (!gic) { + err =3D -ENOMEM; + goto free_irq; + } + gic->handler =3D mana_gd_process_eq_events; INIT_LIST_HEAD(&gic->eq_list); spin_lock_init(&gic->lock); @@ -1418,69 +1493,128 @@ static int mana_gd_setup_irqs(struct pci_dev *pdev) snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_q%d@pci:%s", i - 1, pci_name(pdev)); =20 - irq =3D pci_irq_vector(pdev, i); - if (irq < 0) { - err =3D irq; - goto free_irq; + irqs[i] =3D pci_irq_vector(pdev, i); + if (irqs[i] < 0) { + err =3D irqs[i]; + goto free_current_gic; } =20 - if (!i) { - err =3D request_irq(irq, mana_gd_intr, 0, gic->name, gic); - if (err) - goto free_irq; - - /* If number of IRQ is one extra than number of online CPUs, - * then we need to assign IRQ0 (hwc irq) and IRQ1 to - * same CPU. - * Else we will use different CPUs for IRQ0 and IRQ1. - * Also we are using cpumask_local_spread instead of - * cpumask_first for the node, because the node can be - * mem only. - */ - if (start_irq_index) { - cpu =3D cpumask_local_spread(i, gc->numa_node); - irq_set_affinity_and_hint(irq, cpumask_of(cpu)); - } else { - irqs[start_irq_index] =3D irq; - } - } else { - irqs[i - start_irq_index] =3D irq; - err =3D request_irq(irqs[i - start_irq_index], mana_gd_intr, 0, - gic->name, gic); - if (err) - goto free_irq; - } + err =3D request_irq(irqs[i], mana_gd_intr, 0, gic->name, gic); + if (err) + goto free_current_gic; + + xa_store(&gc->irq_contexts, i, gic, GFP_KERNEL); } =20 - err =3D irq_setup(irqs, nvec - start_irq_index, gc->numa_node, false); - if (err) + /* If number of IRQ is one extra than number of online CPUs, + * then we need to assign IRQ0 (hwc irq) and IRQ1 to + * same CPU. + * Else we will use different CPUs for IRQ0 and IRQ1. + * Also we are using cpumask_local_spread instead of + * cpumask_first for the node, because the node can be + * mem only. + */ + cpus_read_lock(); + if (nvec > num_online_cpus()) { + cpu =3D cpumask_local_spread(0, gc->numa_node); + irq_set_affinity_and_hint(irqs[0], cpumask_of(cpu)); + irqs++; + nvec -=3D 1; + } + + err =3D irq_setup(irqs, nvec, gc->numa_node, false); + if (err) { + cpus_read_unlock(); goto free_irq; + } =20 - gc->max_num_msix =3D nvec; - gc->num_msix_usable =3D nvec; cpus_read_unlock(); - kfree(irqs); + kfree(start_irqs); return 0; =20 +free_current_gic: + kfree(gic); free_irq: - for (j =3D i - 1; j >=3D 0; j--) { - irq =3D pci_irq_vector(pdev, j); - gic =3D &gc->irq_contexts[j]; + for (i -=3D 1; i >=3D 0; i--) { + irq =3D pci_irq_vector(pdev, i); + gic =3D xa_load(&gc->irq_contexts, i); + if (WARN_ON(!gic)) + continue; =20 irq_update_affinity_hint(irq, NULL); free_irq(irq, gic); + xa_erase(&gc->irq_contexts, i); + kfree(gic); } =20 - kfree(gc->irq_contexts); - gc->irq_contexts =3D NULL; -free_irq_array: - kfree(irqs); -free_irq_vector: - cpus_read_unlock(); - pci_free_irq_vectors(pdev); + kfree(start_irqs); return err; } =20 +static int mana_gd_setup_hwc_irqs(struct pci_dev *pdev) +{ + struct gdma_context *gc =3D pci_get_drvdata(pdev); + unsigned int max_irqs, min_irqs; + int nvec, err; + + if (pci_msix_can_alloc_dyn(pdev)) { + max_irqs =3D 1; + min_irqs =3D 1; + } else { + /* Need 1 interrupt for HWC */ + max_irqs =3D min(num_online_cpus(), MANA_MAX_NUM_QUEUES) + 1; + min_irqs =3D 2; + } + + nvec =3D pci_alloc_irq_vectors(pdev, min_irqs, max_irqs, PCI_IRQ_MSIX); + if (nvec < 0) + return nvec; + + err =3D mana_gd_setup_irqs(pdev, nvec); + if (err) { + pci_free_irq_vectors(pdev); + return err; + } + + gc->num_msix_usable =3D nvec; + gc->max_num_msix =3D nvec; + + return 0; +} + +static int mana_gd_setup_remaining_irqs(struct pci_dev *pdev) +{ + struct gdma_context *gc =3D pci_get_drvdata(pdev); + struct msi_map irq_map; + int max_irqs, i, err; + + if (!pci_msix_can_alloc_dyn(pdev)) + /* remain irqs are already allocated with HWC IRQ */ + return 0; + + /* allocate only remaining IRQs*/ + max_irqs =3D gc->num_msix_usable - 1; + + for (i =3D 1; i <=3D max_irqs; i++) { + irq_map =3D pci_msix_alloc_irq_at(pdev, i, NULL); + if (!irq_map.virq) { + err =3D irq_map.index; + /* caller will handle cleaning up all allocated + * irqs, after HWC is destroyed + */ + return err; + } + } + + err =3D mana_gd_setup_dyn_irqs(pdev, max_irqs); + if (err) + return err; + + gc->max_num_msix =3D gc->max_num_msix + max_irqs; + + return 0; +} + static void mana_gd_remove_irqs(struct pci_dev *pdev) { struct gdma_context *gc =3D pci_get_drvdata(pdev); @@ -1495,19 +1629,21 @@ static void mana_gd_remove_irqs(struct pci_dev *pde= v) if (irq < 0) continue; =20 - gic =3D &gc->irq_contexts[i]; + gic =3D xa_load(&gc->irq_contexts, i); + if (WARN_ON(!gic)) + continue; =20 /* Need to clear the hint before free_irq */ irq_update_affinity_hint(irq, NULL); free_irq(irq, gic); + xa_erase(&gc->irq_contexts, i); + kfree(gic); } =20 pci_free_irq_vectors(pdev); =20 gc->max_num_msix =3D 0; gc->num_msix_usable =3D 0; - kfree(gc->irq_contexts); - gc->irq_contexts =3D NULL; } =20 static int mana_gd_setup(struct pci_dev *pdev) @@ -1522,9 +1658,10 @@ static int mana_gd_setup(struct pci_dev *pdev) if (!gc->service_wq) return -ENOMEM; =20 - err =3D mana_gd_setup_irqs(pdev); + err =3D mana_gd_setup_hwc_irqs(pdev); if (err) { - dev_err(gc->dev, "Failed to setup IRQs: %d\n", err); + dev_err(gc->dev, "Failed to setup IRQs for HWC creation: %d\n", + err); goto free_workqueue; } =20 @@ -1540,6 +1677,12 @@ static int mana_gd_setup(struct pci_dev *pdev) if (err) goto destroy_hwc; =20 + err =3D mana_gd_setup_remaining_irqs(pdev); + if (err) { + dev_err(gc->dev, "Failed to setup remaining IRQs: %d", err); + goto destroy_hwc; + } + err =3D mana_gd_detect_devices(pdev); if (err) goto destroy_hwc; @@ -1620,6 +1763,7 @@ static int mana_gd_probe(struct pci_dev *pdev, const = struct pci_device_id *ent) gc->is_pf =3D mana_is_pf(pdev->device); gc->bar0_va =3D bar0_va; gc->dev =3D &pdev->dev; + xa_init(&gc->irq_contexts); =20 if (gc->is_pf) gc->mana_pci_debugfs =3D debugfs_create_dir("0", mana_debugfs_root); @@ -1654,6 +1798,7 @@ static int mana_gd_probe(struct pci_dev *pdev, const = struct pci_device_id *ent) */ debugfs_remove_recursive(gc->mana_pci_debugfs); gc->mana_pci_debugfs =3D NULL; + xa_destroy(&gc->irq_contexts); pci_iounmap(pdev, bar0_va); free_gc: pci_set_drvdata(pdev, NULL); @@ -1679,6 +1824,8 @@ static void mana_gd_remove(struct pci_dev *pdev) =20 gc->mana_pci_debugfs =3D NULL; =20 + xa_destroy(&gc->irq_contexts); + pci_iounmap(pdev, gc->bar0_va); =20 vfree(gc); diff --git a/include/net/mana/gdma.h b/include/net/mana/gdma.h index 3ce56a816425..87162ba96d91 100644 --- a/include/net/mana/gdma.h +++ b/include/net/mana/gdma.h @@ -388,7 +388,7 @@ struct gdma_context { unsigned int max_num_queues; unsigned int max_num_msix; unsigned int num_msix_usable; - struct gdma_irq_context *irq_contexts; + struct xarray irq_contexts; =20 /* L2 MTU */ u16 adapter_mtu; @@ -578,12 +578,16 @@ enum { /* Driver can handle holes (zeros) in the device list */ #define GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP BIT(11) =20 +/* Driver supports dynamic MSI-X vector allocation */ +#define GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT BIT(13) + #define GDMA_DRV_CAP_FLAGS1 \ (GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT | \ GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX | \ GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG | \ GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT | \ - GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP) + GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP | \ + GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT) =20 #define GDMA_DRV_CAP_FLAGS2 0 =20 --=20 2.34.1