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Thu, 22 May 2025 14:43:00 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , , , , , Moshe Shemesh , Mark Bloch , Gal Pressman , Cosmin Ratiu , Dragos Tatulea Subject: [PATCH net-next V2 09/11] net/mlx5e: Add support for UNREADABLE netmem page pools Date: Fri, 23 May 2025 00:41:24 +0300 Message-ID: <1747950086-1246773-10-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1747950086-1246773-1-git-send-email-tariqt@nvidia.com> References: <1747950086-1246773-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CF:EE_|DS2PR12MB9664:EE_ X-MS-Office365-Filtering-Correlation-Id: db75af11-6e8f-4289-babf-08dd9979a96b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?S/fsz7lg6NnIGRKC7MLralCpP9zWMYMszmTmnUfvGQrNlbNhy8FG4luZEKjb?= =?us-ascii?Q?nuYxXNa9FfmRT+EcOC2nPj6qL3RKntrUV+osyCw4qJGY97YWar7SoHRyJ3Dq?= =?us-ascii?Q?2PmX5ippN/cnWRVAR6DQawM1bbSaBCWZ8MM9rW+JTAKe6WbJ6+R8dGhDK6Bk?= =?us-ascii?Q?Jayd1jH2KQQfBzZyIbbfKqK+hoedLWEWILep7ANDIsSexx6mWjCsbWk82sGY?= =?us-ascii?Q?jWB5sW5qH85K3sy6QXxPL43XaIfq9ffeRLZzZhU2vbH0o7H1AURiQheLdgEz?= =?us-ascii?Q?dXhBC5yqGAx18oXR4UTP3IaHCXNqWFohQ0dzXLbEN6dFnqrEuK7Rns2RSWR1?= =?us-ascii?Q?Ag7V+p22f+Ivu/ctJiAADbShw721MFRVn1QbXS3rtlv8K9YE+iqN1EKBI32W?= =?us-ascii?Q?TV0xDGaB7mcF7aObU8UBnYrkSbdoPjJmWYqGakosE8zx13reVTIPd6plrw7x?= =?us-ascii?Q?MmUysgccqEKVIW4yhVxpTbjd0c2dMylV259T8O2EKiDCbvB4knl0uER1YPOJ?= =?us-ascii?Q?S0MNQsfvk7ie3Q80TE9+WGl8ryuPgZBrBUSRcQB3Jgu08vUQLh0MXshGVwKt?= =?us-ascii?Q?c5ccj9hCQxDjQjO5ghbZ3FhUhpVSeu3ZEtxo/I7MNbUJiEZu9vBo2hyoNmfz?= =?us-ascii?Q?lakDXShxXYC12gnBv3U96cije49YPZReEj0haaZjnK81RzwYz1qweqil+LdP?= =?us-ascii?Q?Qk7HVXgSGRQ8d2Y2iOgZUwFstCyJEvNdJ3DoQu2DDrOHQDyUZliioYo2sVwa?= =?us-ascii?Q?2UyLZVKyYqhBfYe/4/EAgJZZk8u3Zpkg9rxbhupf8Dh70Lt0KUCnwzl/fp3B?= =?us-ascii?Q?Jxay1RG/ENYIbLL1779w9m2KIDjXI1neCdc5DsgEUeGcZU1WdMSAP437MQ3d?= =?us-ascii?Q?3s+f6oJ6eElrfDp5s/0/9Rx5UxLGmfBkjRm8h3ANc+vENoa1ARt3y2MQjqDW?= =?us-ascii?Q?f4IrvgSnAgMROLNnXu2Ju7xSEHRgPzHsU6qvk+OBRJAOdyHlp9Whr9uFkUoT?= =?us-ascii?Q?8MaVwnLjG/diE2mwtlt7LhWzc45Ar+tm7MzajEJsCCLOM8zbzue7Yj00imua?= =?us-ascii?Q?Brdu1AIQsVqc06SWw5kM95F36S66zjzz+nHLL7ZW+Bo6tvGTSnFFsdJND1eN?= =?us-ascii?Q?+WCoUp7esLM7BYgDj97d58UXvUV8DIIIVtC3Lccd7NpowWZznAjGJJMg9aG4?= =?us-ascii?Q?f8B8S0WWWAZObNTDazOW8Z5DR5aXe4As4hlQ0dmpGK9mVpqbMEAi43qD46l4?= =?us-ascii?Q?grjSIY1125B7FJPKf/ywgzQ1nqrlrySCt4JNARNEujLRuV1ncOWT74IEa7AM?= =?us-ascii?Q?caethW4RS/pCBqIguRfRAUMRjfHT3ibnL6BL2Y25X0tauUBrKo22WvpUChuA?= =?us-ascii?Q?2iGyZnQMKsaH6wtlqL5T5KiCm8tUqxD86enPhTO/9fbb8lYiV8R2cIjoHp46?= =?us-ascii?Q?11D38VNFE0yJOi0HVDK9zOMC9XLP/3uErmPpwlQXh+O2CqND1KedvzOKFRil?= =?us-ascii?Q?ymzkr86Zxft+bRwK/1w0w17cHV7JKejwY9J8?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 21:43:16.8117 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db75af11-6e8f-4289-babf-08dd9979a96b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9664 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed On netdev_rx_queue_restart, a special type of page pool maybe expected. In this patch declare support for UNREADABLE netmem iov pages in the pool params only when header data split shampo RQ mode is enabled, also set the queue index in the page pool params struct. Shampo mode requirement: Without header split rx needs to peek at the data, we can't do UNREADABLE_NETMEM. Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 9e2975782a82..485b1515ace5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -952,6 +952,11 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, pp_params.netdev =3D rq->netdev; pp_params.dma_dir =3D rq->buff.map_dir; pp_params.max_len =3D PAGE_SIZE; + pp_params.queue_idx =3D rq->ix; + + /* Shampo header data split allow for unreadable netmem */ + if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) + pp_params.flags |=3D PP_FLAG_ALLOW_UNREADABLE_NETMEM; =20 /* page_pool can be used even when there is no rq->xdp_prog, * given page_pool does not handle DMA mapping there is no --=20 2.31.1