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Thu, 22 May 2025 14:42:13 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , , , , , Moshe Shemesh , Mark Bloch , Gal Pressman , Cosmin Ratiu , Dragos Tatulea Subject: [PATCH net-next V2 01/11] net: Kconfig NET_DEVMEM selects GENERIC_ALLOCATOR Date: Fri, 23 May 2025 00:41:16 +0300 Message-ID: <1747950086-1246773-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1747950086-1246773-1-git-send-email-tariqt@nvidia.com> References: <1747950086-1246773-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066E7:EE_|SJ2PR12MB7896:EE_ X-MS-Office365-Filtering-Correlation-Id: e73bf655-bf87-49f5-608f-08dd997990c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ym52WiLZbfU4QYCzSu/rrOY/JAsw9RRFnkj4Q4MBLtTcLtIWrqByCaX2RZLw?= =?us-ascii?Q?HoUudy2Gki8vTKH6X2DunCr/rnSoH91Mg0bXXp6kaO0bgUeSp5i51SEGfQ3V?= =?us-ascii?Q?PiwGYIM0qfQUNv0jd8Uh9+wFOIxWU6LMzRalUzLrPdq9CrsMd0eC1A1QMT61?= =?us-ascii?Q?ntgM02vzVZnSDYu7JMMWKyXcm+6toUSWoOqjpSfwKx2Xn1a/1pAby4O78ye1?= =?us-ascii?Q?JkDudVOYkHbQVPDrdcX5VMkI8Qmy5+GPYLbgzIjRJWClohQ4x6Mk2RxfBUjJ?= =?us-ascii?Q?RUz4U01iK2ZVlzb9R4VbpM468dpDIL2LOoUuwWgpVAIQJmpADPfWNdTYnrv3?= =?us-ascii?Q?Uan0NgdihU+FJRnyHrMaeLkZ88n0q5E1R0FcU4Mje4tTNanifcPnRlv/O5Ew?= =?us-ascii?Q?REi7Y5qSedB8Bej92hN8csZHRym5+CUl4G9GLQ4V2Pb/3FXignms7+HYxTSx?= =?us-ascii?Q?n9LqK3dNmKwFgmudkTbFDE2I8mQxgp/7jdxCks6CiFwU5Qbo2Wd7pR+h37tY?= =?us-ascii?Q?/Ee6FAUeM8+A6adBIBqo4/joNrxeM4QhvzICjXnnQC8yqSYCWtpsHAQmRgUc?= =?us-ascii?Q?E3z/9uVRrm8oYRnZrQAm7qDOzPzs9p+qVmpIEuJTlc8mUgeFW2704qhJeiTX?= =?us-ascii?Q?yPuylku3qUNY/QpOgfOWHUiG1k5D7WqB6wA9dhQQj6uXHeycHkRn4LJmbYJs?= =?us-ascii?Q?gQcWfXwHM8vkVwrGR08a/Uf+FfZLWe2XD9f9YItryTtJJhmvutd/GY3glZM2?= =?us-ascii?Q?Mkvb4mtYmCurZun7sMUG9hGPqQje7goT7F3a6uBXguMsvwWHThHX/WK8ZZ64?= =?us-ascii?Q?UJD3h59t3MVDDP50VFcczPDhSGR4JgFx4et6RKJnk0Abedk+swuXoCLVLaS3?= =?us-ascii?Q?G/tASQYmY3KfbGoL+SYdIWOucSGP9E7QYv5G/nBwfNnbSjI85MwzbCddAhux?= =?us-ascii?Q?uZcpCeScO2H11Puc+PAqJ2FdC77FNVpyHBL58PHptH+E0AjutR/zD+eTwb8n?= =?us-ascii?Q?5sdKOMlCzIo3o7cEF7zDCDqS6pSmWXrLYHYMK4/UkI9F406+Qmevy0t51A5o?= =?us-ascii?Q?XwAiLCnmD5E5f6qoCarkgkueobw825n810ynmxJEpreSUSlMPz18yUTAj58E?= =?us-ascii?Q?wC3kGyM0CoVW0dhw3NgdB4arEl/rTwCwMyAuZUzk2wv3XVbRx46fJq9Qml5h?= =?us-ascii?Q?TWUUbkLY5vhtbjkft9y5VISvF2WKcLSJeMnJ7QH+7o/ECc7nAIRMokrkX3og?= =?us-ascii?Q?maclioY0ElFm4Tcjs51KDK8sh4cIaV0acCuwOIDSMsgAbItvtqd4a5infpa0?= =?us-ascii?Q?Fk64fu40WAhkqEf0/vdiq87rhp+HWRUWawUtkj+diFLjbouzx6xBqnHCdcyd?= =?us-ascii?Q?QXT/FOb74MKDTWd95KGaO2jEUOwtaylHLWCMmbe9HS98gM1UlIDr68Bkge7K?= =?us-ascii?Q?RoZVxY9YMDzWfa5gihVJaGbzWV+wHWRTcj38gG9bw1dBOnd7/o0Isi3BsAdV?= =?us-ascii?Q?vd6IOcwitiTsWePUNsAWLoDn+O2SSvCVv61d?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 21:42:35.3744 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e73bf655-bf87-49f5-608f-08dd997990c1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066E7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7896 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed GENERIC_ALLOCATOR is a non-prompt kconfig, meaning users can't enable it selectively. All kconfig users of GENERIC_ALLOCATOR select it, except of NET_DEVMEM which only depends on it, there is no easy way to turn GENERIC_ALLOCATOR on unless we select other unnecessary configs that will select it. Instead of depending on it, select it when NET_DEVMEM is enabled. Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Mina Almasry --- net/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/Kconfig b/net/Kconfig index 5b71a52987d3..ebc80a98fc91 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -68,8 +68,8 @@ config SKB_EXTENSIONS =20 config NET_DEVMEM def_bool y + select GENERIC_ALLOCATOR depends on DMA_SHARED_BUFFER - depends on GENERIC_ALLOCATOR depends on PAGE_POOL =20 config NET_SHAPER --=20 2.31.1 From nobody Sun Dec 14 06:37:02 2025 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2050.outbound.protection.outlook.com [40.107.220.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1F3B257AF0; Thu, 22 May 2025 21:42:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.50 ARC-Seal: i=2; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , , , , , Moshe Shemesh , Mark Bloch , Gal Pressman , Cosmin Ratiu , Dragos Tatulea Subject: [PATCH net-next V2 02/11] net: Add skb_can_coalesce for netmem Date: Fri, 23 May 2025 00:41:17 +0300 Message-ID: <1747950086-1246773-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1747950086-1246773-1-git-send-email-tariqt@nvidia.com> References: <1747950086-1246773-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|PH7PR12MB9152:EE_ X-MS-Office365-Filtering-Correlation-Id: 46d0492f-2917-4c2b-fa85-08dd9979920d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?waCDSyvyYJvQy9YTyfhnVkzFOMbwLMaRUMK8PZ3Co59T6KXrqdLLG2cBfhb3?= =?us-ascii?Q?YtiGSihCYFhvPdRzhRthaPjmaAyB32k4T6VI+iZ/yahHLZeEyASFjeupaHjU?= =?us-ascii?Q?OJY7847XI3hOX0WjKrAPBnggf8hsCIWJgo5x3jD8LVEOrljfcghpaNtJKDYn?= =?us-ascii?Q?TocAKicrAxkV3pOqwyMgD2+PljlqFYEay9Ots5xUKmOnjoGocoq9PWsPjK9x?= =?us-ascii?Q?KP9qneCPhOcxl0CfuK4dms8Euu/9jJBhYKaJlTAjmzSFB3twRcSRTas8page?= =?us-ascii?Q?SKpt8Zmty9olAgIlQcQFyiU8LdfgonjfhATAsVt0/sW0FWVDx1XIiyEsLICa?= =?us-ascii?Q?TeM40SJYw34CCVCK1DswT9vdeWy6BvVIrQrfj8RVmwnqKm44M/vMhWuIqA+P?= =?us-ascii?Q?CO8jbjE8wi8pUetTbnGE2Y++4jHBU7HWLJ2DAdvnJjA3LZDeAEus7Gf3t86m?= =?us-ascii?Q?m6lDrIOz/xfui+mDO/Zy0UMfVzgK/4MJmXBL3wxvbtdnP5CdSlnnDIAPTCa+?= =?us-ascii?Q?O5yzYVQiSjNAvGPUkbzT0YgKI5ZzwaZNk+jDwUKrK68TB4a5S7ADB79Hq8Qk?= =?us-ascii?Q?sNwxmqnSl/z8Yu+XFo4q1DTQz3nl1/2DvASHPY8jYp3lW8/4pO7D6zPeI/fM?= =?us-ascii?Q?MduOa5pO3Flpv3FQDMWgw7yVHEeaxGf1DOfNd/s3MQ/FPumQbMEJJufcVIp+?= =?us-ascii?Q?ZLF47djhS6QNelw2lFWOZD7ygk7azz++5Pgl4aPT9wUrl5+yszZUcJ4xTqor?= =?us-ascii?Q?jkIro5MkNGUx3l9b1ABVK39/WG0wM2opRK5HYxMyJBISzRGqV7T6FMh9XpKO?= =?us-ascii?Q?ZPp4XfQ0FPdTqESxskzjjDlgTrcfX2OZOH8AOB0od+1xtuBacFELrH2M+eKc?= =?us-ascii?Q?rubwh/XbamiRSGa90skrWVsDZCswOdTZb3czU9XD0xfKACHKdUwKxo+rZMsW?= =?us-ascii?Q?o4ud70gdUAOjQ54EXc2s76bxue+0V6hMafXIAxWe14SPWVrZamFsuEgs4B5q?= =?us-ascii?Q?vGbR7xO5KtiRonQKpMq7DEakAda9gBI0QO62rU5XdRCFgjfnm30DiDf0xXWf?= =?us-ascii?Q?MkTESxDe7s2DconxQ3XV2H2p281GVVmFnoJTMJtmIcBgqt7YpIJyBMeLGfqa?= =?us-ascii?Q?p5fH2/wjwmTjSAbrW9sfnv7yruKarfBxy8WrQl7PweWwRySiQQ3LLE1qhVa7?= =?us-ascii?Q?4hhFp7SrZe6FdHYvJd2Edpu4C/3Ql6J3h8gXC+FvEiTAIgBoTsnl0evGzQbs?= =?us-ascii?Q?dBZ52TdOV9nM+PDojyVyI4uT2XFPwsjkryZdUARs4aXtIrewKhmrcoeLTsH8?= =?us-ascii?Q?pzu4viQ87mMk0MNceLCsWqyDw4LxISeHpecpG9Dmo9YVhXclTtuhHnzvUPgu?= =?us-ascii?Q?i0sk6PUUug1HYhGJysoBVZX9xdLR8396yYMeaBm9MObgXRydqS40S9Yb3uje?= =?us-ascii?Q?vsVaKkxlJcBoSWRHb+hmfFnHJChpneBhm+9+gKpJP2ib0Z+JBzp43ZFk+r5X?= =?us-ascii?Q?v8zLh6/yeVw24/BCtVOMGXVu/7kKjaxBZwcX?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 21:42:37.5521 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 46d0492f-2917-4c2b-fa85-08dd9979920d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9152 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Allow drivers that have moved over to netmem to do fragment coalescing. Signed-off-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- include/linux/skbuff.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index 5520524c93bf..e8e2860183b4 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -3887,6 +3887,18 @@ static inline bool skb_can_coalesce(struct sk_buff *= skb, int i, return false; } =20 +static inline bool skb_can_coalesce_netmem(struct sk_buff *skb, int i, + const netmem_ref netmem, int off) +{ + if (i) { + const skb_frag_t *frag =3D &skb_shinfo(skb)->frags[i - 1]; + + return netmem =3D=3D skb_frag_netmem(frag) && + off =3D=3D skb_frag_off(frag) + skb_frag_size(frag); + } + return false; +} + static inline int __skb_linearize(struct sk_buff *skb) { return __pskb_pull_tail(skb, skb->data_len) ? 0 : -ENOMEM; --=20 2.31.1 From nobody Sun Dec 14 06:37:02 2025 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2070.outbound.protection.outlook.com [40.107.102.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A52F24A06C; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , , , , , Moshe Shemesh , Mark Bloch , Gal Pressman , Cosmin Ratiu , Dragos Tatulea Subject: [PATCH net-next V2 03/11] net/mlx5e: SHAMPO: Reorganize mlx5_rq_shampo_alloc Date: Fri, 23 May 2025 00:41:18 +0300 Message-ID: <1747950086-1246773-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1747950086-1246773-1-git-send-email-tariqt@nvidia.com> References: <1747950086-1246773-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D0:EE_|DM6PR12MB4186:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f1df692-4f0e-45ae-ec3f-08dd99799733 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Mh118qY/Y0ZT38lyI5eA9ErQpcHGSEackGMencFblzl/ENakcJDkW34d83JP?= =?us-ascii?Q?3Z0gprU/qKfykijhZJycy6DrWGw4q5ZHXMtINaGitECO5wHVKP26oYKjwzMf?= =?us-ascii?Q?ZXli2taravvY/nJri9yJcHhej3jg3FHwaQKxJid04s2ARm3/HBq8gcfYCSkA?= =?us-ascii?Q?U2mxWASskt/rXxXE4GegzaarOuKn1onZo+JT31Xjl58e1BJE16SJDqbwlqao?= =?us-ascii?Q?bMsyLI8l94fVEQzdBOpLPk5PaEhI6BKPKUyQo0rEvknGhR05nEWhhHhwpUP5?= =?us-ascii?Q?l9ti6fjJOyQ9Pi0RhCSH3tpH2FiE8ffltufNPGT0giRR/v8qoMIrrSG5KmIb?= =?us-ascii?Q?lmjrxinT8TXMuzUAZmWW3CCozp2EWTBcG8plExhCMF64z2B5QGOces2c6NAY?= =?us-ascii?Q?OFGgyxnNCFpssGPW1N1OkFoxX7n/QHjBhOTOB1ewRh5gIfCHG0wdgetFR87D?= =?us-ascii?Q?Wg6yFuMSi6UEzQjv/iKqSXIHUXuK7ndPhPSqouBr1OGPgQNNy32DSte/i9yA?= =?us-ascii?Q?QZ/wUpC+eSRyezg0FTPFmVKgQfnZgI4SfFGR35URDcDo6NrbGEGqs09ZCX6F?= =?us-ascii?Q?CYtNJ293shDv7b/tbH5uQS8wETrPSe9NJKqN8QdipRrXHBOs2GK+wYWGl+fi?= =?us-ascii?Q?43lqDeZ4VldxBz/TNiDFL7e6uRduBpxU2Mxj8oAJcrj7rM8xzBuyH9mwPljz?= =?us-ascii?Q?6mUWV4NvkAEd4gWEOvbrWQa5u+1c5gegbPz+3P6ZQd4rJMGUBEC2RsQNpkmQ?= =?us-ascii?Q?7xantuF24gwygI/msxYZ9idD1lYorcFZq1OQgOgwwCUAPwl1AhExbr/LvJzN?= =?us-ascii?Q?XJVbx/kmaZouzuXu2L5iKioXw9o3yzqm1ix015K2tiyEaxNr3lt6knNiHbgu?= =?us-ascii?Q?Jtu2Se2M+qtTMfz3iX4mH+twPrDi6ZzOsT8IWxEjfkfgKVrche+/xz4KxDW5?= =?us-ascii?Q?OSOPd/rSwSMkznguD5gRWI3FUf0nnQ5/Fw+LNTTFqjZfxYyBm04x/Nq1qJT9?= =?us-ascii?Q?Zp/ZVTg/xrRHTVaWNYyHX4xViiurdEHIZK5otDDzBILY27B+j8CKW6VUyaUw?= =?us-ascii?Q?rDbprz5r53x5SoY3mLCRUYyp7sKbegud9pBnx+iMaM5zQoOzSlIJJEzeU3qT?= =?us-ascii?Q?SCZ56i8WyksLKLM/hQm7liwjiZ/ENPFie13BhXmlYbn/iGcsKtdIt3Fytw86?= =?us-ascii?Q?Wly5ajftxgahuZXCSUfoSm0jcHsWOGRCFGTamy9kc/sE9/H7vykOVNLepIth?= =?us-ascii?Q?PtfhwvWsYJmmoaL/1urakpZsn09GTincNEDOcHVuwbnLm2pDVnYF/eWC8uV5?= =?us-ascii?Q?2BzyNzyRdArB/Xuncum90v/8NT6kUj3B9TzYb4bdlhoKli4P7VN92i0CFagF?= =?us-ascii?Q?vDkC+1lDKsYrrIMyq1o82naitNqVCi2/GPJ8eap7VoTp4f2+uyM5ARBtj6pa?= =?us-ascii?Q?Bkx1useCWuw9ivXLPoyuT8Ew8o8s6FM1wkssLUdvft0J9jWzniTbJ5c++FXA?= =?us-ascii?Q?f6GSyS69JBxi01LN6JKYGqwoiMe1KlIuULqM?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 21:42:46.1989 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f1df692-4f0e-45ae-ec3f-08dd99799733 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4186 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed Drop redundant SHAMPO structure alloc/free functions. Gather together function calls pertaining to header split info, pass header per WQE (hd_per_wqe) as parameter to those function to avoid use before initialization future mistakes. Allocate HW GRO related info outside of the header related info scope. Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 - .../net/ethernet/mellanox/mlx5/core/en_main.c | 135 +++++++++--------- 2 files changed, 66 insertions(+), 70 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 5b0d03b3efe8..211ea429ea89 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -638,7 +638,6 @@ struct mlx5e_shampo_hd { struct mlx5e_frag_page *pages; u32 hd_per_wq; u16 hd_per_wqe; - u16 pages_per_wq; unsigned long *bitmap; u16 pi; u16 ci; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index ea822c69d137..3d11c9f87171 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -331,47 +331,6 @@ static inline void mlx5e_build_umr_wqe(struct mlx5e_rq= *rq, ucseg->mkey_mask =3D cpu_to_be64(MLX5_MKEY_MASK_FREE); } =20 -static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node) -{ - rq->mpwqe.shampo =3D kvzalloc_node(sizeof(*rq->mpwqe.shampo), - GFP_KERNEL, node); - if (!rq->mpwqe.shampo) - return -ENOMEM; - return 0; -} - -static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq) -{ - kvfree(rq->mpwqe.shampo); -} - -static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node) -{ - struct mlx5e_shampo_hd *shampo =3D rq->mpwqe.shampo; - - shampo->bitmap =3D bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL, - node); - shampo->pages =3D kvzalloc_node(array_size(shampo->hd_per_wq, - sizeof(*shampo->pages)), - GFP_KERNEL, node); - if (!shampo->bitmap || !shampo->pages) - goto err_nomem; - - return 0; - -err_nomem: - bitmap_free(shampo->bitmap); - kvfree(shampo->pages); - - return -ENOMEM; -} - -static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq) -{ - bitmap_free(rq->mpwqe.shampo->bitmap); - kvfree(rq->mpwqe.shampo->pages); -} - static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node) { int wq_sz =3D mlx5_wq_ll_get_size(&rq->mpwqe.wq); @@ -584,19 +543,18 @@ static int mlx5e_create_rq_umr_mkey(struct mlx5_core_= dev *mdev, struct mlx5e_rq } =20 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev, - struct mlx5e_rq *rq) + u16 hd_per_wq, u32 *umr_mkey) { u32 max_ksm_size =3D BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size)); =20 - if (max_ksm_size < rq->mpwqe.shampo->hd_per_wq) { + if (max_ksm_size < hd_per_wq) { mlx5_core_err(mdev, "max ksm list size 0x%x is smaller than shampo heade= r buffer list size 0x%x\n", - max_ksm_size, rq->mpwqe.shampo->hd_per_wq); + max_ksm_size, hd_per_wq); return -EINVAL; } - - return mlx5e_create_umr_ksm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq, + return mlx5e_create_umr_ksm_mkey(mdev, hd_per_wq, MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE, - &rq->mpwqe.shampo->mkey); + umr_mkey); } =20 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq) @@ -758,6 +716,35 @@ static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, = struct mlx5e_params *param xdp_frag_size); } =20 +static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, u16 hd_per_w= q, + int node) +{ + struct mlx5e_shampo_hd *shampo =3D rq->mpwqe.shampo; + + shampo->hd_per_wq =3D hd_per_wq; + + shampo->bitmap =3D bitmap_zalloc_node(hd_per_wq, GFP_KERNEL, node); + shampo->pages =3D kvzalloc_node(array_size(hd_per_wq, + sizeof(*shampo->pages)), + GFP_KERNEL, node); + if (!shampo->bitmap || !shampo->pages) + goto err_nomem; + + return 0; + +err_nomem: + kvfree(shampo->pages); + bitmap_free(shampo->bitmap); + + return -ENOMEM; +} + +static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq) +{ + kvfree(rq->mpwqe.shampo->pages); + bitmap_free(rq->mpwqe.shampo->bitmap); +} + static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_rq_param *rqp, @@ -765,42 +752,52 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev = *mdev, u32 *pool_size, int node) { + void *wqc =3D MLX5_ADDR_OF(rqc, rqp->rqc, wq); + u16 hd_per_wq; + int wq_size; int err; =20 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) return 0; - err =3D mlx5e_rq_shampo_hd_alloc(rq, node); - if (err) - goto out; - rq->mpwqe.shampo->hd_per_wq =3D - mlx5e_shampo_hd_per_wq(mdev, params, rqp); - err =3D mlx5e_create_rq_hd_umr_mkey(mdev, rq); + + rq->mpwqe.shampo =3D kvzalloc_node(sizeof(*rq->mpwqe.shampo), + GFP_KERNEL, node); + if (!rq->mpwqe.shampo) + return -ENOMEM; + + /* split headers data structures */ + hd_per_wq =3D mlx5e_shampo_hd_per_wq(mdev, params, rqp); + err =3D mlx5e_rq_shampo_hd_info_alloc(rq, hd_per_wq, node); if (err) - goto err_shampo_hd; - err =3D mlx5e_rq_shampo_hd_info_alloc(rq, node); + goto err_shampo_hd_info_alloc; + + err =3D mlx5e_create_rq_hd_umr_mkey(mdev, hd_per_wq, + &rq->mpwqe.shampo->mkey); if (err) - goto err_shampo_info; + goto err_umr_mkey; + + rq->mpwqe.shampo->key =3D cpu_to_be32(rq->mpwqe.shampo->mkey); + rq->mpwqe.shampo->hd_per_wqe =3D + mlx5e_shampo_hd_per_wqe(mdev, params, rqp); + wq_size =3D BIT(MLX5_GET(wq, wqc, log_wq_sz)); + *pool_size +=3D (rq->mpwqe.shampo->hd_per_wqe * wq_size) / + MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; + + /* gro only data structures */ rq->hw_gro_data =3D kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, n= ode); if (!rq->hw_gro_data) { err =3D -ENOMEM; goto err_hw_gro_data; } - rq->mpwqe.shampo->key =3D - cpu_to_be32(rq->mpwqe.shampo->mkey); - rq->mpwqe.shampo->hd_per_wqe =3D - mlx5e_shampo_hd_per_wqe(mdev, params, rqp); - rq->mpwqe.shampo->pages_per_wq =3D - rq->mpwqe.shampo->hd_per_wq / MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; - *pool_size +=3D rq->mpwqe.shampo->pages_per_wq; + return 0; =20 err_hw_gro_data: - mlx5e_rq_shampo_hd_info_free(rq); -err_shampo_info: mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey); -err_shampo_hd: - mlx5e_rq_shampo_hd_free(rq); -out: +err_umr_mkey: + mlx5e_rq_shampo_hd_info_free(rq); +err_shampo_hd_info_alloc: + kvfree(rq->mpwqe.shampo); return err; } =20 @@ -812,7 +809,7 @@ static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq) kvfree(rq->hw_gro_data); mlx5e_rq_shampo_hd_info_free(rq); mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey); - mlx5e_rq_shampo_hd_free(rq); + kvfree(rq->mpwqe.shampo); } =20 static int mlx5e_alloc_rq(struct mlx5e_params *params, --=20 2.31.1 From nobody Sun Dec 14 06:37:02 2025 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2082.outbound.protection.outlook.com [40.107.220.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93A8925B66D; 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Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 4 --- .../ethernet/mellanox/mlx5/core/en/params.c | 36 ++++++++++--------- .../net/ethernet/mellanox/mlx5/core/en_main.c | 4 --- 3 files changed, 20 insertions(+), 24 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 211ea429ea89..581eef34f512 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -278,10 +278,6 @@ enum packet_merge { struct mlx5e_packet_merge_param { enum packet_merge type; u32 timeout; - struct { - u8 match_criteria_type; - u8 alignment_granularity; - } shampo; }; =20 struct mlx5e_params { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index 58ec5e44aa7a..fc945bce933a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -901,6 +901,7 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, { void *rqc =3D param->rqc; void *wq =3D MLX5_ADDR_OF(rqc, rqc, wq); + u32 lro_timeout; int ndsegs =3D 1; int err; =20 @@ -926,22 +927,25 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, MLX5_SET(wq, wq, log_wqe_stride_size, log_wqe_stride_size - MLX5_MPWQE_LOG_STRIDE_SZ_BASE); MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(mdev, params, xs= k)); - if (params->packet_merge.type =3D=3D MLX5E_PACKET_MERGE_SHAMPO) { - MLX5_SET(wq, wq, shampo_enable, true); - MLX5_SET(wq, wq, log_reservation_size, - mlx5e_shampo_get_log_rsrv_size(mdev, params)); - MLX5_SET(wq, wq, - log_max_num_of_packets_per_reservation, - mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); - MLX5_SET(wq, wq, log_headers_entry_size, - mlx5e_shampo_get_log_hd_entry_size(mdev, params)); - MLX5_SET(rqc, rqc, reservation_timeout, - mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_SHAMPO_TIMEOUT)); - MLX5_SET(rqc, rqc, shampo_match_criteria_type, - params->packet_merge.shampo.match_criteria_type); - MLX5_SET(rqc, rqc, shampo_no_match_alignment_granularity, - params->packet_merge.shampo.alignment_granularity); - } + if (params->packet_merge.type !=3D MLX5E_PACKET_MERGE_SHAMPO) + break; + + MLX5_SET(wq, wq, shampo_enable, true); + MLX5_SET(wq, wq, log_reservation_size, + mlx5e_shampo_get_log_rsrv_size(mdev, params)); + MLX5_SET(wq, wq, + log_max_num_of_packets_per_reservation, + mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); + MLX5_SET(wq, wq, log_headers_entry_size, + mlx5e_shampo_get_log_hd_entry_size(mdev, params)); + lro_timeout =3D + mlx5e_choose_lro_timeout(mdev, + MLX5E_DEFAULT_SHAMPO_TIMEOUT); + MLX5_SET(rqc, rqc, reservation_timeout, lro_timeout); + MLX5_SET(rqc, rqc, shampo_match_criteria_type, + MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED); + MLX5_SET(rqc, rqc, shampo_no_match_alignment_granularity, + MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE); break; } default: /* MLX5_WQ_TYPE_CYCLIC */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 3d11c9f87171..e1e44533b744 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -4040,10 +4040,6 @@ static int set_feature_hw_gro(struct net_device *net= dev, bool enable) =20 if (enable) { new_params.packet_merge.type =3D MLX5E_PACKET_MERGE_SHAMPO; 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No functional change here as all by default disabled features are explicitly disabled at the bottom of the function. Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index e1e44533b744..a81d354af7c8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -78,7 +78,8 @@ =20 static bool mlx5e_hw_gro_supported(struct mlx5_core_dev *mdev) { - if (!MLX5_CAP_GEN(mdev, shampo)) + if (!MLX5_CAP_GEN(mdev, shampo) || + !MLX5_CAP_SHAMPO(mdev, shampo_header_split_data_merge)) return false; =20 /* Our HW-GRO implementation relies on "KSM Mkey" for @@ -5499,17 +5500,17 @@ static void mlx5e_build_nic_netdev(struct net_devic= e *netdev) MLX5E_MPWRQ_UMR_MODE_ALIGNED)) netdev->vlan_features |=3D NETIF_F_LRO; =20 + if (mlx5e_hw_gro_supported(mdev) && + mlx5e_check_fragmented_striding_rq_cap(mdev, PAGE_SHIFT, + MLX5E_MPWRQ_UMR_MODE_ALIGNED)) + netdev->vlan_features |=3D NETIF_F_GRO_HW; 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This will be useful for adding support to zc page pool, which has to be different from the headers page pool. Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 4 ++ .../net/ethernet/mellanox/mlx5/core/en_main.c | 37 ++++++++++++++--- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 41 +++++++++++-------- 3 files changed, 59 insertions(+), 23 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 581eef34f512..c329de1d4f0a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -716,7 +716,11 @@ struct mlx5e_rq { struct bpf_prog __rcu *xdp_prog; struct mlx5e_xdpsq *xdpsq; DECLARE_BITMAP(flags, 8); + + /* page pools */ struct page_pool *page_pool; + struct page_pool *hd_page_pool; + struct mlx5e_xdp_buff mxbuf; =20 /* AF_XDP zero-copy */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index a81d354af7c8..9e2975782a82 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -750,12 +750,10 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev = *mdev, struct mlx5e_params *params, struct mlx5e_rq_param *rqp, struct mlx5e_rq *rq, - u32 *pool_size, int node) { void *wqc =3D MLX5_ADDR_OF(rqc, rqp->rqc, wq); u16 hd_per_wq; - int wq_size; int err; =20 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) @@ -780,9 +778,33 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *= mdev, rq->mpwqe.shampo->key =3D cpu_to_be32(rq->mpwqe.shampo->mkey); rq->mpwqe.shampo->hd_per_wqe =3D mlx5e_shampo_hd_per_wqe(mdev, params, rqp); - wq_size =3D BIT(MLX5_GET(wq, wqc, log_wq_sz)); - *pool_size +=3D (rq->mpwqe.shampo->hd_per_wqe * wq_size) / - MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; + + /* separate page pool for shampo headers */ + { + int wq_size =3D BIT(MLX5_GET(wq, wqc, log_wq_sz)); + struct page_pool_params pp_params =3D { }; + u32 pool_size; + + pool_size =3D (rq->mpwqe.shampo->hd_per_wqe * wq_size) / + MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; + + pp_params.order =3D 0; + pp_params.flags =3D PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; + pp_params.pool_size =3D pool_size; + pp_params.nid =3D node; + pp_params.dev =3D rq->pdev; + pp_params.napi =3D rq->cq.napi; + pp_params.netdev =3D rq->netdev; + pp_params.dma_dir =3D rq->buff.map_dir; + pp_params.max_len =3D PAGE_SIZE; + + rq->hd_page_pool =3D page_pool_create(&pp_params); + if (IS_ERR(rq->hd_page_pool)) { + err =3D PTR_ERR(rq->hd_page_pool); + rq->hd_page_pool =3D NULL; + goto err_hds_page_pool; + } + } =20 /* gro only data structures */ rq->hw_gro_data =3D kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, n= ode); @@ -794,6 +816,8 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *m= dev, return 0; =20 err_hw_gro_data: + page_pool_destroy(rq->hd_page_pool); +err_hds_page_pool: mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey); err_umr_mkey: mlx5e_rq_shampo_hd_info_free(rq); @@ -808,6 +832,7 @@ static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq) return; =20 kvfree(rq->hw_gro_data); + page_pool_destroy(rq->hd_page_pool); mlx5e_rq_shampo_hd_info_free(rq); mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey); kvfree(rq->mpwqe.shampo); @@ -887,7 +912,7 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, if (err) goto err_rq_mkey; =20 - err =3D mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node); + err =3D mlx5_rq_shampo_alloc(mdev, params, rqp, rq, node); if (err) goto err_free_mpwqe_info; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index 84b1ab8233b8..e34ef53ebd0e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -273,12 +273,12 @@ static inline u32 mlx5e_decompress_cqes_start(struct = mlx5e_rq *rq, =20 #define MLX5E_PAGECNT_BIAS_MAX (PAGE_SIZE / 64) =20 -static int mlx5e_page_alloc_fragmented(struct mlx5e_rq *rq, +static int mlx5e_page_alloc_fragmented(struct page_pool *pool, struct mlx5e_frag_page *frag_page) { struct page *page; =20 - page =3D page_pool_dev_alloc_pages(rq->page_pool); + page =3D page_pool_dev_alloc_pages(pool); if (unlikely(!page)) return -ENOMEM; =20 @@ -292,14 +292,14 @@ static int mlx5e_page_alloc_fragmented(struct mlx5e_r= q *rq, return 0; } =20 -static void mlx5e_page_release_fragmented(struct mlx5e_rq *rq, +static void mlx5e_page_release_fragmented(struct page_pool *pool, struct mlx5e_frag_page *frag_page) { u16 drain_count =3D MLX5E_PAGECNT_BIAS_MAX - frag_page->frags; struct page *page =3D frag_page->page; =20 if (page_pool_unref_page(page, drain_count) =3D=3D 0) - page_pool_put_unrefed_page(rq->page_pool, page, -1, true); + page_pool_put_unrefed_page(pool, page, -1, true); } =20 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq, @@ -313,7 +313,8 @@ static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq, * offset) should just use the new one without replenishing again * by themselves. */ - err =3D mlx5e_page_alloc_fragmented(rq, frag->frag_page); + err =3D mlx5e_page_alloc_fragmented(rq->page_pool, + frag->frag_page); =20 return err; } @@ -332,7 +333,7 @@ static inline void mlx5e_put_rx_frag(struct mlx5e_rq *r= q, struct mlx5e_wqe_frag_info *frag) { if (mlx5e_frag_can_release(frag)) - mlx5e_page_release_fragmented(rq, frag->frag_page); + mlx5e_page_release_fragmented(rq->page_pool, frag->frag_page); } =20 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u1= 6 ix) @@ -584,7 +585,8 @@ mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_m= pw_info *wi) struct mlx5e_frag_page *frag_page; =20 frag_page =3D &wi->alloc_units.frag_pages[i]; - mlx5e_page_release_fragmented(rq, frag_page); + mlx5e_page_release_fragmented(rq->page_pool, + frag_page); } } } @@ -679,11 +681,10 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq = *rq, struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, i= ndex); u64 addr; =20 - err =3D mlx5e_page_alloc_fragmented(rq, frag_page); + err =3D mlx5e_page_alloc_fragmented(rq->hd_page_pool, frag_page); if (unlikely(err)) goto err_unmap; =20 - addr =3D page_pool_get_dma_addr(frag_page->page); =20 for (int j =3D 0; j < MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; j++) { @@ -715,7 +716,8 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *r= q, if (!header_offset) { struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, = index); =20 - mlx5e_page_release_fragmented(rq, frag_page); + mlx5e_page_release_fragmented(rq->hd_page_pool, + frag_page); } } =20 @@ -791,7 +793,7 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u1= 6 ix) for (i =3D 0; i < rq->mpwqe.pages_per_wqe; i++, frag_page++) { dma_addr_t addr; =20 - err =3D mlx5e_page_alloc_fragmented(rq, frag_page); + err =3D mlx5e_page_alloc_fragmented(rq->page_pool, frag_page); if (unlikely(err)) goto err_unmap; addr =3D page_pool_get_dma_addr(frag_page->page); @@ -836,7 +838,7 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u1= 6 ix) err_unmap: while (--i >=3D 0) { frag_page--; - mlx5e_page_release_fragmented(rq, frag_page); + mlx5e_page_release_fragmented(rq->page_pool, frag_page); } =20 bitmap_fill(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe); @@ -855,7 +857,7 @@ mlx5e_free_rx_shampo_hd_entry(struct mlx5e_rq *rq, u16 = header_index) if (((header_index + 1) & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1)) =3D=3D 0= ) { struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, h= eader_index); =20 - mlx5e_page_release_fragmented(rq, frag_page); + mlx5e_page_release_fragmented(rq->hd_page_pool, frag_page); } clear_bit(header_index, shampo->bitmap); } @@ -1100,6 +1102,8 @@ INDIRECT_CALLABLE_SCOPE bool mlx5e_post_rx_mpwqes(str= uct mlx5e_rq *rq) =20 if (rq->page_pool) page_pool_nid_changed(rq->page_pool, numa_mem_id()); + if (rq->hd_page_pool) + page_pool_nid_changed(rq->hd_page_pool, numa_mem_id()); =20 head =3D rq->mpwqe.actual_wq_head; i =3D missing; @@ -2004,7 +2008,8 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *r= q, struct mlx5e_mpw_info *w if (prog) { /* area for bpf_xdp_[store|load]_bytes */ net_prefetchw(page_address(frag_page->page) + frag_offset); - if (unlikely(mlx5e_page_alloc_fragmented(rq, &wi->linear_page))) { + if (unlikely(mlx5e_page_alloc_fragmented(rq->page_pool, + &wi->linear_page))) { rq->stats->buff_alloc_err++; return NULL; } @@ -2068,7 +2073,8 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *r= q, struct mlx5e_mpw_info *w =20 wi->linear_page.frags++; } - mlx5e_page_release_fragmented(rq, &wi->linear_page); + mlx5e_page_release_fragmented(rq->page_pool, + &wi->linear_page); return NULL; /* page/packet was consumed by XDP */ } =20 @@ -2077,13 +2083,14 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq = *rq, struct mlx5e_mpw_info *w mxbuf->xdp.data - mxbuf->xdp.data_hard_start, 0, mxbuf->xdp.data - mxbuf->xdp.data_meta); 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Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_stats.c | 53 +++++++++++++++++++ .../ethernet/mellanox/mlx5/core/en_stats.h | 24 +++++++++ 2 files changed, 77 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/n= et/ethernet/mellanox/mlx5/core/en_stats.c index 19664fa7f217..dcfe86d6dc83 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -205,6 +205,18 @@ static const struct counter_desc sw_stats_desc[] =3D { { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_ring) }, { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_ring_full) }, { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_released_ref) }, + + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_hd_alloc_fast) }, + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_hd_alloc_slow) }, + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_hd_alloc_slow_high_orde= r) }, + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_hd_alloc_empty) }, + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_hd_alloc_refill) }, + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_hd_alloc_waive) }, + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_hd_recycle_cached) }, + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_hd_recycle_cache_full) = }, + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_hd_recycle_ring) }, + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_hd_recycle_ring_full) }, + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_hd_recycle_released_ref= ) }, #ifdef CONFIG_MLX5_EN_TLS { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_decrypted_packets) }, { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_decrypted_bytes) }, @@ -384,6 +396,18 @@ static void mlx5e_stats_grp_sw_update_stats_rq_stats(s= truct mlx5e_sw_stats *s, s->rx_pp_recycle_ring +=3D rq_stats->pp_recycle_ring; s->rx_pp_recycle_ring_full +=3D rq_stats->pp_recycle_ring_full; s->rx_pp_recycle_released_ref +=3D rq_stats->pp_recycle_released_ref; + + s->rx_pp_hd_alloc_fast +=3D rq_stats->pp_hd_alloc_fast; + s->rx_pp_hd_alloc_slow +=3D rq_stats->pp_hd_alloc_slow; + s->rx_pp_hd_alloc_empty +=3D rq_stats->pp_hd_alloc_empty; + s->rx_pp_hd_alloc_refill +=3D rq_stats->pp_hd_alloc_refill; + s->rx_pp_hd_alloc_waive +=3D rq_stats->pp_hd_alloc_waive; + s->rx_pp_hd_alloc_slow_high_order +=3D rq_stats->pp_hd_alloc_slow_high_or= der; + s->rx_pp_hd_recycle_cached +=3D rq_stats->pp_hd_recycle_cached; + s->rx_pp_hd_recycle_cache_full +=3D rq_stats->pp_hd_recycle_cache_full; + s->rx_pp_hd_recycle_ring +=3D rq_stats->pp_hd_recycle_ring; + s->rx_pp_hd_recycle_ring_full +=3D rq_stats->pp_hd_recycle_ring_full; + s->rx_pp_hd_recycle_released_ref +=3D rq_stats->pp_hd_recycle_released_re= f; #ifdef CONFIG_MLX5_EN_TLS s->rx_tls_decrypted_packets +=3D rq_stats->tls_decrypted_packets; s->rx_tls_decrypted_bytes +=3D rq_stats->tls_decrypted_bytes; @@ -511,6 +535,23 @@ static void mlx5e_stats_update_stats_rq_page_pool(stru= ct mlx5e_channel *c) rq_stats->pp_recycle_ring =3D stats.recycle_stats.ring; rq_stats->pp_recycle_ring_full =3D stats.recycle_stats.ring_full; rq_stats->pp_recycle_released_ref =3D stats.recycle_stats.released_refcnt; + + pool =3D c->rq.hd_page_pool; + if (!pool || !page_pool_get_stats(pool, &stats)) + return; + + rq_stats->pp_hd_alloc_fast =3D stats.alloc_stats.fast; + rq_stats->pp_hd_alloc_slow =3D stats.alloc_stats.slow; + rq_stats->pp_hd_alloc_slow_high_order =3D stats.alloc_stats.slow_high_ord= er; + rq_stats->pp_hd_alloc_empty =3D stats.alloc_stats.empty; + rq_stats->pp_hd_alloc_waive =3D stats.alloc_stats.waive; + rq_stats->pp_hd_alloc_refill =3D stats.alloc_stats.refill; + + rq_stats->pp_hd_recycle_cached =3D stats.recycle_stats.cached; + rq_stats->pp_hd_recycle_cache_full =3D stats.recycle_stats.cache_full; + rq_stats->pp_hd_recycle_ring =3D stats.recycle_stats.ring; + rq_stats->pp_hd_recycle_ring_full =3D stats.recycle_stats.ring_full; + rq_stats->pp_hd_recycle_released_ref =3D stats.recycle_stats.released_ref= cnt; } =20 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(sw) @@ -2130,6 +2171,18 @@ static const struct counter_desc rq_stats_desc[] =3D= { { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_ring) }, { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_ring_full) }, { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_released_ref) }, + + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_hd_alloc_fast) }, + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_hd_alloc_slow) }, + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_hd_alloc_slow_high_orde= r) }, + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_hd_alloc_empty) }, + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_hd_alloc_refill) }, + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_hd_alloc_waive) }, + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_hd_recycle_cached) }, + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_hd_recycle_cache_full) = }, + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_hd_recycle_ring) }, + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_hd_recycle_ring_full) }, + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_hd_recycle_released_ref= ) }, #ifdef CONFIG_MLX5_EN_TLS { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_decrypted_packets) }, { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_decrypted_bytes) }, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h b/drivers/n= et/ethernet/mellanox/mlx5/core/en_stats.h index def5dea1463d..113221dfcdfa 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h @@ -226,6 +226,18 @@ struct mlx5e_sw_stats { u64 rx_pp_recycle_ring; u64 rx_pp_recycle_ring_full; u64 rx_pp_recycle_released_ref; + + u64 rx_pp_hd_alloc_fast; + u64 rx_pp_hd_alloc_slow; + u64 rx_pp_hd_alloc_slow_high_order; + u64 rx_pp_hd_alloc_empty; + u64 rx_pp_hd_alloc_refill; + u64 rx_pp_hd_alloc_waive; + u64 rx_pp_hd_recycle_cached; + u64 rx_pp_hd_recycle_cache_full; + u64 rx_pp_hd_recycle_ring; + u64 rx_pp_hd_recycle_ring_full; + u64 rx_pp_hd_recycle_released_ref; #ifdef CONFIG_MLX5_EN_TLS u64 tx_tls_encrypted_packets; u64 tx_tls_encrypted_bytes; @@ -394,6 +406,18 @@ struct mlx5e_rq_stats { u64 pp_recycle_ring; u64 pp_recycle_ring_full; u64 pp_recycle_released_ref; + + u64 pp_hd_alloc_fast; + u64 pp_hd_alloc_slow; + u64 pp_hd_alloc_slow_high_order; + u64 pp_hd_alloc_empty; + u64 pp_hd_alloc_refill; + u64 pp_hd_alloc_waive; + u64 pp_hd_recycle_cached; + u64 pp_hd_recycle_cache_full; + u64 pp_hd_recycle_ring; + u64 pp_hd_recycle_ring_full; + u64 pp_hd_recycle_released_ref; #ifdef CONFIG_MLX5_EN_TLS u64 tls_decrypted_packets; u64 tls_decrypted_bytes; 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Thu, 22 May 2025 14:42:54 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , , , , , Moshe Shemesh , Mark Bloch , Gal Pressman , Cosmin Ratiu , Dragos Tatulea Subject: [PATCH net-next V2 08/11] net/mlx5e: Convert over to netmem Date: Fri, 23 May 2025 00:41:23 +0300 Message-ID: <1747950086-1246773-9-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1747950086-1246773-1-git-send-email-tariqt@nvidia.com> References: <1747950086-1246773-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|CY3PR12MB9680:EE_ X-MS-Office365-Filtering-Correlation-Id: 303b0706-b777-4a87-f79c-08dd9979a618 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?FpOjHMZ8QM2z7uxMO2dJlTGn5oI313S2NIgFWPUxfd6yJQH0cMsrvtPrwPAt?= =?us-ascii?Q?bzaMNCnr0X5oydWb98mE8oPl5YdoeZhKgB07eGb2sfZcg9kJEO/tbNW1EUoN?= =?us-ascii?Q?bLMrtXvDcipyX54rbrS/o4DP2lJSVtjlEjN+FbbWcwKpfxYvKwwRSUm0O5Pm?= =?us-ascii?Q?vEGFgb6VhUJEdFEzltm/ymqEG2CrxhXCpuhT/aEDfj45uVRJ1JjLCN6ZhslF?= =?us-ascii?Q?0AThEA3mhOC4pMNIOtdF1ZCUXGshJjZ3gHqBB4GLDepeMTtzieDwfIB13yOM?= =?us-ascii?Q?oliYvqVCphAA+39wJ4FkAO8acLPR0MwklIES/ZeAsuzvwpxDJjKDyghIjrAc?= =?us-ascii?Q?sdD4r9m94xEbnSwlS5Yer3kYD0Gb4IM/Uk0eyiJB/356uMTutTr2nIP7nakq?= =?us-ascii?Q?XoNdpgW1SPGQTCM939j2i4gZ87jJD1q7kRrYJghQwOatSy4baHyRlcNkBmbW?= =?us-ascii?Q?MLs6RVlJU9dxB03Z3OicqUdUhSgmA2khcIXwqhblW8flIxZJ1XVzY+E09mqX?= =?us-ascii?Q?1XuvlvDA3SuDPXoGejPLUHqazHYrPjj88PIqSUolACFfQhSQz+fh8fcg91d3?= =?us-ascii?Q?b23XSzhfT+XjIngNqHNEYtI16PfWb8xVDlhbJpAwENFnMJoBi1tLhoaM4lZ+?= =?us-ascii?Q?Xudye0QmewRD2SvRKW2edcznDTL8d61S4S1Ewy2Tkv/GGY/4gVoqMafwg0n0?= =?us-ascii?Q?nmX4y53BkGrhT6dYeIoaf1BidIaUxi175LBimRgxmTEOT9XAZupzqo9cOTEj?= =?us-ascii?Q?YQbvLzQMMWTOodCtGY1HriZV8lfBTOswh3C1Dib3YocT4oxMouSDstSG3cbR?= =?us-ascii?Q?/RC0MfjI2jLUt0JxPV7l268GCblV098v37ucumX08UQG9rFsfN55lwpuS56L?= =?us-ascii?Q?so5jZZEPmjal5ueJOo0mdw1AL9FNz5NcxZaaBpinj0ugL/KvjYk+LbMSXRx+?= =?us-ascii?Q?UZe0GP5FWhBCoJfRNqSB+VCoD+JL4GGc3LLj5alAzT6B1pwEOax1E5DComcq?= =?us-ascii?Q?3KhWCcaYkwQlQ2L/6asUNG8FRW9pFOQny3/7cL09T7q17V7qwxUc9ygQHtSP?= =?us-ascii?Q?KJ7FIrHFvTovppq1+mCPgnChMxuZ6vtaLZjoTB9XGfMyWnoYqkvhgRVUpMWv?= =?us-ascii?Q?CUyeyaJmo5dB6bm6Ng9evKAMBU0ovrcQGz1AyaKh1CFgn8k8t0Dd1AWyhv2k?= =?us-ascii?Q?WpuSZQNBPWm45uZLndhaZHhuPKCL7k/mCVJ0dQ3pOCpFMNR6fFRGrBriYC9z?= =?us-ascii?Q?AKvPLNkeGnB+0+qlY1TP95pliES+deUk4zYyFZJOhOQae6ehkonMU4Dd/D1H?= =?us-ascii?Q?AlpU6tl9DGa3VyVqnHGToHcPhQEyxRXVCWgmSgR66Y3EUnlhrcvUKVRWPkJf?= =?us-ascii?Q?cRtEOML65m3W6PMj9x2VNg7w2iwJ9Qv+MFV2DdHoUbVCJbcGINKM0tGn4waU?= =?us-ascii?Q?/OPxxA0y5ZQyf8L7ewbflCPk+j6f6x0k75jio5HGRYJrR/c6WXEPcFquVsjw?= =?us-ascii?Q?3hZutSoKd/HWZQIqf2FPtjzDtauYK3uBHPdH?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 21:43:11.1787 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 303b0706-b777-4a87-f79c-08dd9979a618 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9680 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed mlx5e_page_frag holds the physical page itself, to naturally support zc page pools, remove physical page reference from mlx5 and replace it with netmem_ref, to avoid internal handling in mlx5 for net_iov backed pages. SHAMPO can issue packets that are not split into header and data. These packets will be dropped if the data part resides in a net_iov as the driver can't read into this area. No performance degradation observed. Signed-off-by: Saeed Mahameed Signed-off-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 2 +- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 103 ++++++++++-------- 2 files changed, 61 insertions(+), 44 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index c329de1d4f0a..65a73913b9a2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -553,7 +553,7 @@ struct mlx5e_icosq { } ____cacheline_aligned_in_smp; =20 struct mlx5e_frag_page { - struct page *page; + netmem_ref netmem; u16 frags; }; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index e34ef53ebd0e..75e753adedef 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -273,33 +273,33 @@ static inline u32 mlx5e_decompress_cqes_start(struct = mlx5e_rq *rq, =20 #define MLX5E_PAGECNT_BIAS_MAX (PAGE_SIZE / 64) =20 -static int mlx5e_page_alloc_fragmented(struct page_pool *pool, +static int mlx5e_page_alloc_fragmented(struct page_pool *pp, struct mlx5e_frag_page *frag_page) { - struct page *page; + netmem_ref netmem =3D page_pool_alloc_netmems(pp, + GFP_ATOMIC | __GFP_NOWARN); =20 - page =3D page_pool_dev_alloc_pages(pool); - if (unlikely(!page)) + if (unlikely(!netmem)) return -ENOMEM; =20 - page_pool_fragment_page(page, MLX5E_PAGECNT_BIAS_MAX); + page_pool_fragment_netmem(netmem, MLX5E_PAGECNT_BIAS_MAX); =20 *frag_page =3D (struct mlx5e_frag_page) { - .page =3D page, + .netmem =3D netmem, .frags =3D 0, }; =20 return 0; } =20 -static void mlx5e_page_release_fragmented(struct page_pool *pool, +static void mlx5e_page_release_fragmented(struct page_pool *pp, struct mlx5e_frag_page *frag_page) { u16 drain_count =3D MLX5E_PAGECNT_BIAS_MAX - frag_page->frags; - struct page *page =3D frag_page->page; + netmem_ref netmem =3D frag_page->netmem; =20 - if (page_pool_unref_page(page, drain_count) =3D=3D 0) - page_pool_put_unrefed_page(pool, page, -1, true); + if (page_pool_unref_netmem(netmem, drain_count) =3D=3D 0) + page_pool_put_unrefed_netmem(pp, netmem, -1, true); } =20 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq, @@ -359,7 +359,7 @@ static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, stru= ct mlx5e_rx_wqe_cyc *wqe, frag->flags &=3D ~BIT(MLX5E_WQE_FRAG_SKIP_RELEASE); =20 headroom =3D i =3D=3D 0 ? rq->buff.headroom : 0; - addr =3D page_pool_get_dma_addr(frag->frag_page->page); + addr =3D page_pool_get_dma_addr_netmem(frag->frag_page->netmem); wqe->data[i].addr =3D cpu_to_be64(addr + frag->offset + headroom); } =20 @@ -500,9 +500,10 @@ mlx5e_add_skb_shared_info_frag(struct mlx5e_rq *rq, st= ruct skb_shared_info *sinf struct xdp_buff *xdp, struct mlx5e_frag_page *frag_page, u32 frag_offset, u32 len) { + netmem_ref netmem =3D frag_page->netmem; skb_frag_t *frag; =20 - dma_addr_t addr =3D page_pool_get_dma_addr(frag_page->page); + dma_addr_t addr =3D page_pool_get_dma_addr_netmem(netmem); =20 dma_sync_single_for_cpu(rq->pdev, addr + frag_offset, len, rq->buff.map_d= ir); if (!xdp_buff_has_frags(xdp)) { @@ -515,9 +516,9 @@ mlx5e_add_skb_shared_info_frag(struct mlx5e_rq *rq, str= uct skb_shared_info *sinf } =20 frag =3D &sinfo->frags[sinfo->nr_frags++]; - skb_frag_fill_page_desc(frag, frag_page->page, frag_offset, len); + skb_frag_fill_netmem_desc(frag, netmem, frag_offset, len); =20 - if (page_is_pfmemalloc(frag_page->page)) + if (!netmem_is_net_iov(netmem) && netmem_is_pfmemalloc(netmem)) xdp_buff_set_frag_pfmemalloc(xdp); sinfo->xdp_frags_size +=3D len; } @@ -528,27 +529,29 @@ mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buf= f *skb, u32 frag_offset, u32 len, unsigned int truesize) { - dma_addr_t addr =3D page_pool_get_dma_addr(frag_page->page); + dma_addr_t addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); u8 next_frag =3D skb_shinfo(skb)->nr_frags; + netmem_ref netmem =3D frag_page->netmem; =20 dma_sync_single_for_cpu(rq->pdev, addr + frag_offset, len, rq->buff.map_dir); =20 - if (skb_can_coalesce(skb, next_frag, frag_page->page, frag_offset)) { + if (skb_can_coalesce_netmem(skb, next_frag, netmem, frag_offset)) { skb_coalesce_rx_frag(skb, next_frag - 1, len, truesize); - } else { - frag_page->frags++; - skb_add_rx_frag(skb, next_frag, frag_page->page, - frag_offset, len, truesize); + return; } + + frag_page->frags++; + skb_add_rx_frag_netmem(skb, next_frag, netmem, + frag_offset, len, truesize); } =20 static inline void mlx5e_copy_skb_header(struct mlx5e_rq *rq, struct sk_buff *skb, - struct page *page, dma_addr_t addr, + netmem_ref netmem, dma_addr_t addr, int offset_from, int dma_offset, u32 headlen) { - const void *from =3D page_address(page) + offset_from; + const void *from =3D netmem_address(netmem) + offset_from; /* Aligning len to sizeof(long) optimizes memcpy performance */ unsigned int len =3D ALIGN(headlen, sizeof(long)); =20 @@ -685,7 +688,7 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *r= q, if (unlikely(err)) goto err_unmap; =20 - addr =3D page_pool_get_dma_addr(frag_page->page); + addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); =20 for (int j =3D 0; j < MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; j++) { header_offset =3D mlx5e_shampo_hd_offset(index++); @@ -796,7 +799,8 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u1= 6 ix) err =3D mlx5e_page_alloc_fragmented(rq->page_pool, frag_page); if (unlikely(err)) goto err_unmap; - addr =3D page_pool_get_dma_addr(frag_page->page); + + addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); umr_wqe->inline_mtts[i] =3D (struct mlx5_mtt) { .ptag =3D cpu_to_be64(addr | MLX5_EN_WR), }; @@ -1216,7 +1220,7 @@ static void *mlx5e_shampo_get_packet_hd(struct mlx5e_= rq *rq, u16 header_index) struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, he= ader_index); u16 head_offset =3D mlx5e_shampo_hd_offset(header_index) + rq->buff.headr= oom; =20 - return page_address(frag_page->page) + head_offset; + return netmem_address(frag_page->netmem) + head_offset; } =20 static void mlx5e_shampo_update_ipv4_udp_hdr(struct mlx5e_rq *rq, struct i= phdr *ipv4) @@ -1677,11 +1681,11 @@ mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, stru= ct mlx5e_wqe_frag_info *wi, dma_addr_t addr; u32 frag_size; =20 - va =3D page_address(frag_page->page) + wi->offset; + va =3D netmem_address(frag_page->netmem) + wi->offset; data =3D va + rx_headroom; frag_size =3D MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); =20 - addr =3D page_pool_get_dma_addr(frag_page->page); + addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); dma_sync_single_range_for_cpu(rq->pdev, addr, wi->offset, frag_size, rq->buff.map_dir); net_prefetch(data); @@ -1731,10 +1735,10 @@ mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, s= truct mlx5e_wqe_frag_info *wi =20 frag_page =3D wi->frag_page; =20 - va =3D page_address(frag_page->page) + wi->offset; + va =3D netmem_address(frag_page->netmem) + wi->offset; frag_consumed_bytes =3D min_t(u32, frag_info->frag_size, cqe_bcnt); =20 - addr =3D page_pool_get_dma_addr(frag_page->page); + addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); dma_sync_single_range_for_cpu(rq->pdev, addr, wi->offset, rq->buff.frame0_sz, rq->buff.map_dir); net_prefetchw(va); /* xdp_frame data area */ @@ -2007,13 +2011,14 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq = *rq, struct mlx5e_mpw_info *w =20 if (prog) { /* area for bpf_xdp_[store|load]_bytes */ - net_prefetchw(page_address(frag_page->page) + frag_offset); + net_prefetchw(netmem_address(frag_page->netmem) + frag_offset); if (unlikely(mlx5e_page_alloc_fragmented(rq->page_pool, &wi->linear_page))) { rq->stats->buff_alloc_err++; return NULL; } - va =3D page_address(wi->linear_page.page); + + va =3D netmem_address(wi->linear_page.netmem); net_prefetchw(va); /* xdp_frame data area */ linear_hr =3D XDP_PACKET_HEADROOM; linear_data_len =3D 0; @@ -2124,8 +2129,8 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *r= q, struct mlx5e_mpw_info *w while (++pagep < frag_page); } /* copy header */ - addr =3D page_pool_get_dma_addr(head_page->page); - mlx5e_copy_skb_header(rq, skb, head_page->page, addr, + addr =3D page_pool_get_dma_addr_netmem(head_page->netmem); + mlx5e_copy_skb_header(rq, skb, head_page->netmem, addr, head_offset, head_offset, headlen); /* skb linear part was allocated with headlen and aligned to long */ skb->tail +=3D headlen; @@ -2155,11 +2160,11 @@ mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq= , struct mlx5e_mpw_info *wi, return NULL; } =20 - va =3D page_address(frag_page->page) + head_offset; + va =3D netmem_address(frag_page->netmem) + head_offset; data =3D va + rx_headroom; frag_size =3D MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); =20 - addr =3D page_pool_get_dma_addr(frag_page->page); + addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); dma_sync_single_range_for_cpu(rq->pdev, addr, head_offset, frag_size, rq->buff.map_dir); net_prefetch(data); @@ -2198,16 +2203,19 @@ mlx5e_skb_from_cqe_shampo(struct mlx5e_rq *rq, stru= ct mlx5e_mpw_info *wi, struct mlx5_cqe64 *cqe, u16 header_index) { struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, he= ader_index); - dma_addr_t page_dma_addr =3D page_pool_get_dma_addr(frag_page->page); u16 head_offset =3D mlx5e_shampo_hd_offset(header_index); - dma_addr_t dma_addr =3D page_dma_addr + head_offset; u16 head_size =3D cqe->shampo.header_size; u16 rx_headroom =3D rq->buff.headroom; struct sk_buff *skb =3D NULL; + dma_addr_t page_dma_addr; + dma_addr_t dma_addr; void *hdr, *data; u32 frag_size; =20 - hdr =3D page_address(frag_page->page) + head_offset; + page_dma_addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); + dma_addr =3D page_dma_addr + head_offset; + + hdr =3D netmem_address(frag_page->netmem) + head_offset; data =3D hdr + rx_headroom; frag_size =3D MLX5_SKB_FRAG_SZ(rx_headroom + head_size); =20 @@ -2232,7 +2240,7 @@ mlx5e_skb_from_cqe_shampo(struct mlx5e_rq *rq, struct= mlx5e_mpw_info *wi, } =20 net_prefetchw(skb->data); - mlx5e_copy_skb_header(rq, skb, frag_page->page, dma_addr, + mlx5e_copy_skb_header(rq, skb, frag_page->netmem, dma_addr, head_offset + rx_headroom, rx_headroom, head_size); /* skb linear part was allocated with headlen and aligned to long */ @@ -2326,11 +2334,20 @@ static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct= mlx5e_rq *rq, struct mlx5_cq } =20 if (!*skb) { - if (likely(head_size)) + if (likely(head_size)) { *skb =3D mlx5e_skb_from_cqe_shampo(rq, wi, cqe, header_index); - else - *skb =3D mlx5e_skb_from_cqe_mpwrq_nonlinear(rq, wi, cqe, cqe_bcnt, - data_offset, page_idx); + } else { + struct mlx5e_frag_page *frag_page; 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In this patch declare support for UNREADABLE netmem iov pages in the pool params only when header data split shampo RQ mode is enabled, also set the queue index in the page pool params struct. Shampo mode requirement: Without header split rx needs to peek at the data, we can't do UNREADABLE_NETMEM. Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 9e2975782a82..485b1515ace5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -952,6 +952,11 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, pp_params.netdev =3D rq->netdev; pp_params.dma_dir =3D rq->buff.map_dir; pp_params.max_len =3D PAGE_SIZE; + pp_params.queue_idx =3D rq->ix; + + /* Shampo header data split allow for unreadable netmem */ + if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) + pp_params.flags |=3D PP_FLAG_ALLOW_UNREADABLE_NETMEM; =20 /* page_pool can be used even when there is no rq->xdp_prog, * given page_pool does not handle DMA mapping there is no --=20 2.31.1 From nobody Sun Dec 14 06:37:02 2025 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2074.outbound.protection.outlook.com [40.107.220.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BEA02580CF; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , , , , , Moshe Shemesh , Mark Bloch , Gal Pressman , Cosmin Ratiu , Dragos Tatulea Subject: [PATCH net-next V2 10/11] net/mlx5e: Implement queue mgmt ops and single channel swap Date: Fri, 23 May 2025 00:41:25 +0300 Message-ID: <1747950086-1246773-11-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1747950086-1246773-1-git-send-email-tariqt@nvidia.com> References: <1747950086-1246773-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000014:EE_|PH8PR12MB6988:EE_ X-MS-Office365-Filtering-Correlation-Id: 3093ed20-b42f-4019-85f2-08dd9979ad63 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?fmVG6E0uB02lNdqKrRVB/1X+u1q+vjf0+K6sGBGAcaSHpWUhnuPCeRe3ferQ?= =?us-ascii?Q?ujS0qJOV8DwcWuoKnV8qYoPLDcGjJhQ8M0oh56yUe5+epxvOfVxQchq6z7In?= =?us-ascii?Q?jwdIqjBhIJuFvHz8Ci6NkXYa67MF4BYNehi7vMVmI82XN/Oju55arYjmGo86?= =?us-ascii?Q?eyXmrF8zzQAusZNARJkP5Kdo0gb3XNRoOpPg2s0ws+q004uELoG1XjvjCIWg?= =?us-ascii?Q?0Moa5k61TjlGAYodO9lTOPU9VSa+lisFn6NBtlZDgs4vXcqsDZCE4Mfnk0yA?= =?us-ascii?Q?IQD1kzrtgE8ije6l7FDjHcqBmdlYQCF+9lAaK6gJTUOQiwJtqh9hHTirCdWe?= =?us-ascii?Q?DxKsSWTnNaEXBkYtSOqyf9/Ycqsenzox4uBu0XQ4D4Q9YZO7duX04HZf7gjp?= =?us-ascii?Q?jS9HDKKU1gC+FwHooGh3W6ldnSkoEel96wWY9+6dkoEaPOKtMETekip89hL9?= =?us-ascii?Q?JVlcbyHCXu7FEVRJzYLNu6TBfPLkzaXhw7t+YjakCXob8VYUwAMH3dQtHscH?= =?us-ascii?Q?M+7KKO+fbh1jX9wK47Xlq0MEd1Pe1LaaCKUTH444BM/377OPyCtgknXHBD3q?= =?us-ascii?Q?qSJZptQD+sojRnjesBrW1o+97ybatwm/UCHhWH03f3f1IAXXuJNQkfVe6Cfi?= =?us-ascii?Q?Oef8OfGT6ySjYvD1DF5xMnwv7avs4dWbfSjZuyBenCy+gSVsklAwRQTLsl9c?= =?us-ascii?Q?6eOzwwbERseQ9rkytd5kout03KAZLf90E/G7hfiTNZH0cZRgseAmPcR2kNOl?= =?us-ascii?Q?r2K/kIK2vX/Lz2ZFqRL7LlV+HRSq+86L9aANtlTgatYdwcyO6+GWM/WLI/u9?= =?us-ascii?Q?zUHNYz3ImEA0PoxnfyexYtin45KPNsftJn01Q3yK4BolKz4GxCM0tnBHR/Jh?= =?us-ascii?Q?X7iYsMherBjFeffHDLyMahsdirBF4bDN8jo4uaOuUfO18xJmd7rCKWjGFP7h?= =?us-ascii?Q?6q6cokHAcjv7kUbYwFzDvv2mo0yLNvmU25UeNtP2irE/UAjuT2iD/noxEqsX?= =?us-ascii?Q?MX8HU76pJhqMbH8p2pltFedAItSfQ86O9soMnie2o6n6trYsNn6CTl2xbPtt?= =?us-ascii?Q?uvM7JgUpZ2uWO3zzg/Zz7ANlGu5o0kQ2OvW6Of/f3f9oMQptTmf/Fq6YLlw7?= =?us-ascii?Q?tf/kUowLNNNMUkuceyHBecZszdKteoMOwQjqx/Su43vPHCwIxKIXUvy1SH2l?= =?us-ascii?Q?Pn7d1ZU/XVl1e5vJB9zeryNMM0IE5LvGnLeR+v/zVDO1LE+yPVyot3LeULZc?= =?us-ascii?Q?v+BW3A1n90yPS2/7vNgRsPly52CPOG+Bl/DfpyScWtm6pPC+h2zf8fv6Up97?= =?us-ascii?Q?7e8vVb2HFYyMf0sPHagqXIKf6UTpIT4yUX4kpqSp6K78SKj1d+DUergcALbB?= =?us-ascii?Q?onXfYOtZIwMlERIUzYnycRzVFxn+IG1MvJk18N6TGUZubeqo9BJJwFc2KKpt?= =?us-ascii?Q?qF2gmCDv4yNJx2R5ZKDs4ZWkqojNzKAoi/pyKpq+n5RsNfvTFasEVc3Wr9j/?= =?us-ascii?Q?zM0F8ez1gixcfHcyVzleo+o0OFbxM/9e+Tli?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 21:43:23.4064 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3093ed20-b42f-4019-85f2-08dd9979ad63 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000014.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6988 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed The bulk of the work is done in mlx5e_queue_mem_alloc, where we allocate and create the new channel resources, similar to mlx5e_safe_switch_params, but here we do it for a single channel using existing params, sort of a clone channel. To swap the old channel with the new one, we deactivate and close the old channel then replace it with the new one, since the swap procedure doesn't fail in mlx5, we do it all in one place (mlx5e_queue_start). Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_main.c | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 485b1515ace5..3cc316ace0a5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -5478,6 +5478,100 @@ static const struct netdev_stat_ops mlx5e_stat_ops = =3D { .get_base_stats =3D mlx5e_get_base_stats, }; =20 +struct mlx5_qmgmt_data { + struct mlx5e_channel *c; + struct mlx5e_channel_param cparam; +}; + +static int mlx5e_queue_mem_alloc(struct net_device *dev, void *newq, + int queue_index) +{ + struct mlx5_qmgmt_data *new =3D (struct mlx5_qmgmt_data *)newq; + struct mlx5e_priv *priv =3D netdev_priv(dev); + struct mlx5e_channels *chs =3D &priv->channels; + struct mlx5e_params params =3D chs->params; + struct mlx5_core_dev *mdev; + int err; + + mutex_lock(&priv->state_lock); + if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { + err =3D -ENODEV; + goto unlock; + } + + if (queue_index >=3D chs->num) { + err =3D -ERANGE; + goto unlock; + } + + if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || + chs->params.ptp_rx || + chs->params.xdp_prog || + priv->htb) { + netdev_err(priv->netdev, + "Cloning channels with Port/rx PTP, XDP or HTB is not supported\n"); + err =3D -EOPNOTSUPP; + goto unlock; + } + + mdev =3D mlx5_sd_ch_ix_get_dev(priv->mdev, queue_index); + err =3D mlx5e_build_channel_param(mdev, ¶ms, &new->cparam); + if (err) + goto unlock; + + err =3D mlx5e_open_channel(priv, queue_index, ¶ms, NULL, &new->c); +unlock: + mutex_unlock(&priv->state_lock); + return err; +} + +static void mlx5e_queue_mem_free(struct net_device *dev, void *mem) +{ + struct mlx5_qmgmt_data *data =3D (struct mlx5_qmgmt_data *)mem; + + /* not supposed to happen since mlx5e_queue_start never fails + * but this is how this should be implemented just in case + */ + if (data->c) + mlx5e_close_channel(data->c); +} + +static int mlx5e_queue_stop(struct net_device *dev, void *oldq, int queue_= index) +{ + /* mlx5e_queue_start does not fail, we stop the old queue there */ + return 0; +} + +static int mlx5e_queue_start(struct net_device *dev, void *newq, + int queue_index) +{ + struct mlx5_qmgmt_data *new =3D (struct mlx5_qmgmt_data *)newq; + struct mlx5e_priv *priv =3D netdev_priv(dev); + struct mlx5e_channel *old; + + mutex_lock(&priv->state_lock); + + /* stop and close the old */ + old =3D priv->channels.c[queue_index]; + mlx5e_deactivate_priv_channels(priv); + /* close old before activating new, to avoid napi conflict */ + mlx5e_close_channel(old); + + /* start the new */ + priv->channels.c[queue_index] =3D new->c; + mlx5e_activate_priv_channels(priv); + mutex_unlock(&priv->state_lock); + return 0; +} + +static const struct netdev_queue_mgmt_ops mlx5e_queue_mgmt_ops =3D { + .ndo_queue_mem_size =3D sizeof(struct mlx5_qmgmt_data), + .ndo_queue_mem_alloc =3D mlx5e_queue_mem_alloc, + .ndo_queue_mem_free =3D mlx5e_queue_mem_free, + .ndo_queue_start =3D mlx5e_queue_start, + .ndo_queue_stop =3D mlx5e_queue_stop, +}; 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Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers= /net/ethernet/mellanox/mlx5/core/en_ethtool.c index ea078c9f5d15..b6c3b6c11f86 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -371,6 +371,14 @@ void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *pr= iv, (priv->channels.params.packet_merge.type =3D=3D MLX5E_PACKET_MERGE_SHAMP= O) ? ETHTOOL_TCP_DATA_SPLIT_ENABLED : ETHTOOL_TCP_DATA_SPLIT_DISABLED; + + /* if HW GRO is not enabled due to external limitations but is wanted, + * report HDS state as unknown so it won't get turned off explicitly. + */ + if (kernel_param->tcp_data_split =3D=3D ETHTOOL_TCP_DATA_SPLIT_DISABLED && + priv->netdev->wanted_features & NETIF_F_GRO_HW) + kernel_param->tcp_data_split =3D ETHTOOL_TCP_DATA_SPLIT_UNKNOWN; + } =20 static void mlx5e_get_ringparam(struct net_device *dev, @@ -383,6 +391,43 @@ static void mlx5e_get_ringparam(struct net_device *dev, mlx5e_ethtool_get_ringparam(priv, param, kernel_param); } =20 +static bool mlx5e_ethtool_set_tcp_data_split(struct mlx5e_priv *priv, + u8 tcp_data_split) +{ + bool enable =3D (tcp_data_split =3D=3D ETHTOOL_TCP_DATA_SPLIT_ENABLED); + struct net_device *dev =3D priv->netdev; + + if (tcp_data_split =3D=3D ETHTOOL_TCP_DATA_SPLIT_UNKNOWN) + return true; + + if (enable && !(dev->hw_features & NETIF_F_GRO_HW)) { + netdev_warn(dev, "TCP-data-split is not supported when GRO HW is not sup= ported\n"); + return false; /* GRO HW is not supported */ + } + + if (enable && (dev->features & NETIF_F_GRO_HW)) { + /* Already enabled */ + dev->wanted_features |=3D NETIF_F_GRO_HW; + return true; + } + + if (!enable && !(dev->features & NETIF_F_GRO_HW)) { + /* Already disabled */ + dev->wanted_features &=3D ~NETIF_F_GRO_HW; + return true; + } + + /* Try enable or disable GRO HW */ + if (enable) + dev->wanted_features |=3D NETIF_F_GRO_HW; + else + dev->wanted_features &=3D ~NETIF_F_GRO_HW; + + netdev_change_features(dev); + + return enable =3D=3D !!(dev->features & NETIF_F_GRO_HW); +} + int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, struct ethtool_ringparam *param, struct netlink_ext_ack *extack) @@ -441,6 +486,10 @@ static int mlx5e_set_ringparam(struct net_device *dev, { struct mlx5e_priv *priv =3D netdev_priv(dev); =20 + if (!mlx5e_ethtool_set_tcp_data_split(priv, + kernel_param->tcp_data_split)) + return -EINVAL; + return mlx5e_ethtool_set_ringparam(priv, param, extack); } =20 @@ -2625,6 +2674,7 @@ const struct ethtool_ops mlx5e_ethtool_ops =3D { ETHTOOL_COALESCE_USE_ADAPTIVE | ETHTOOL_COALESCE_USE_CQE, .supported_input_xfrm =3D RXH_XFRM_SYM_OR_XOR, + .supported_ring_params =3D ETHTOOL_RING_USE_TCP_DATA_SPLIT, .get_drvinfo =3D mlx5e_get_drvinfo, .get_link =3D ethtool_op_get_link, .get_link_ext_state =3D mlx5e_get_link_ext_state, --=20 2.31.1