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Wed, 21 May 2025 23:28:41 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Tariq Toukan , "Leon Romanovsky" , , , , Moshe Shemesh , Mark Bloch , Gal Pressman Subject: [PATCH net 1/2] net/mlx5: Ensure fw pages are always allocated on same NUMA Date: Thu, 22 May 2025 09:28:05 +0300 Message-ID: <1747895286-1075233-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1747895286-1075233-1-git-send-email-tariqt@nvidia.com> References: <1747895286-1075233-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A102:EE_|BL1PR12MB5923:EE_ X-MS-Office365-Filtering-Correlation-Id: 314932ed-ab48-404d-755c-08dd98f9ef23 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ys82Wl6FtdNHzD8m0T6F9ZeM50MeVOkUxwsx5GgisEiCgWYBrorUUMXL8PK1?= =?us-ascii?Q?Csni9aZsatk8LFtlU1KOXVGCOm3yWtsD4I2IDtb02XluqwaqPPZwv4fFST+k?= =?us-ascii?Q?DmmxPooO9RBOL+zJpRq0P/Dpynjep/DO0BnJCtsDABhO+X8Vq6ZDnZ0LM8Ic?= =?us-ascii?Q?bMXWlZxsbsUnJAZNoCn7VrIWDOkcQ1I6ltvo6cV4NIzRzGU1gC6ZcksZ2NBR?= =?us-ascii?Q?nzyBpMj8/+s7ONoQUPn7NSYoOrK9SprSeDyy6DbzP6XGJ6hn7laKr3XKJ77V?= =?us-ascii?Q?HeSLhX6ppUS29yVXaQsFCrkV2iu+n8l2rwTvob3pbZKmmxVqDnRvTu0ghiZb?= =?us-ascii?Q?++VSNzgdB8yvasDP21I55EnWwSE83ISXHXRds+x0BniqVttGSQiK3HRjIaeV?= =?us-ascii?Q?FXsJ0vS0m+sZFl1t9BTNTr80pFwCyxAwA8Zc1P9YgjtryDhOj9lYFPnQn33k?= =?us-ascii?Q?7Y/UWxhJASTgSyyTT4vpCX+ooL021LNvey9E/asBDaGl6KhXG8iBlZ9+Eni1?= =?us-ascii?Q?WkPNh9Gtk5/TyHvpOKJhitRKYZaqutDsssTXjsjLVmiBGAzh2ZVf8WzXsnmw?= =?us-ascii?Q?lagypuGZJMMUdD8u6kEcMsISNmMo/xAD0njo25vUCVcWejkGz/FP6MEEHjw8?= =?us-ascii?Q?MMc08KQts4F+5GpWVXC7tFu4V76asx3FtWXHHMUrjzsFrZFutRB0sQu4ruTe?= =?us-ascii?Q?OcTlw4APo+gshqPT9Xpd7Iy9FueBCKxhpZJdYc+24iA6AV+oI9RmAkPAEYrt?= =?us-ascii?Q?CIPICKGEvgPNP2VRfQ02sbpf4Qryux3Ct6OV5SgQkIjBs94qtrogKE5btt/e?= =?us-ascii?Q?ElZz6naDbTXmueWSM0NWfnR2TF0jOqci1TvzAR6ATofXNcHXT0RBNCYsEafj?= =?us-ascii?Q?sV0IVxNS3qJNHX6cCJKyCxqzQqHaILBvKBrR9bkS2TL4Fs4FBk3N/Gp+HgX0?= =?us-ascii?Q?gYhsmE80rPu09kOhdZWUmIn2LnPb012tp1TRz5y5QGnBxF6edPf/z4QOpEY/?= =?us-ascii?Q?6T84fgdQdeoH1GxlnULdf9/VrD6fZL22RmG+ad6y5I5IlJHBPWkv9cxJWgqU?= =?us-ascii?Q?JhaB222PAUcWoildslxtdhDpM90iF0gS0+NXuuHoHgNrvRGYpx2FTsnVVupx?= =?us-ascii?Q?bJA89yr1QCjBZIU1cEn3Df/faAU+pZOe/1HyvC0IAPVHlGkF1kJ2pA0hRE/2?= =?us-ascii?Q?CnXd+fgutMnvmOXPQbPCS+aJf6qI8TqfgX47HTx0l8ZObC1dkahzMi+AVNnS?= =?us-ascii?Q?1+SArrvpvze5WCpOJ4xs+6vDapUkt4MaiAWT1LUpGp0rRvRQXkgtBOhvVmr0?= =?us-ascii?Q?JygAxArf8SVdHG05C08L34xNYzqnudXoMz5W3unGe1XJpWy13lu4QaR9Gj9N?= =?us-ascii?Q?0fKbGIPp3Skc9uppXHub3Zkzfk8vPeAVpvJgoijMbRAoeO2cu+rVxyulSV1Z?= =?us-ascii?Q?+f+QWgKdTEiDVaHM5PDmwiUVTGLM1vsJhf+bkJW5db9Ob9QDkKjtETuO7P9U?= =?us-ascii?Q?LxknWae9ww45KhEHlH2lZ8aEXrvXIpUf1llQ?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 06:28:58.0828 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 314932ed-ab48-404d-755c-08dd98f9ef23 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5923 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh When firmware asks the driver to allocate more pages, using event of give_pages, the driver should always allocate it from same NUMA, the original device NUMA. Current code uses dev_to_node() which can result in different NUMA as it is changed by other driver flows, such as mlx5_dma_zalloc_coherent_node(). Instead, use saved numa node for allocating firmware pages. Fixes: 311c7c71c9bb ("net/mlx5e: Allocate DMA coherent memory on reader NUM= A node") Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan Reviewed-by: Dawid Osuchowski --- drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c b/drivers/= net/ethernet/mellanox/mlx5/core/pagealloc.c index 972e8e9df585..9bc9bd83c232 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c @@ -291,7 +291,7 @@ static void free_4k(struct mlx5_core_dev *dev, u64 addr= , u32 function) static int alloc_system_page(struct mlx5_core_dev *dev, u32 function) { struct device *device =3D mlx5_core_dma_dev(dev); - int nid =3D dev_to_node(device); + int nid =3D dev->priv.numa_node; struct page *page; u64 zero_addr =3D 1; u64 addr; --=20 2.31.1 From nobody Sun Dec 14 12:17:06 2025 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2065.outbound.protection.outlook.com [40.107.223.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43BFA221FC3; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Tariq Toukan , "Leon Romanovsky" , , , , Moshe Shemesh , Mark Bloch , Gal Pressman , Jianbo Liu Subject: [PATCH net 2/2] net/mlx5e: Fix leak of Geneve TLV option object Date: Thu, 22 May 2025 09:28:06 +0300 Message-ID: <1747895286-1075233-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1747895286-1075233-1-git-send-email-tariqt@nvidia.com> References: <1747895286-1075233-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A102:EE_|PH7PR12MB6418:EE_ X-MS-Office365-Filtering-Correlation-Id: 52831330-b224-4c97-a279-08dd98f9f201 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Rvhiu8T5s13eYqB8rZ8G+k2e09U7CXbqtoyU4igNCpZ/k94mMzUUfJKCuwOY?= =?us-ascii?Q?/RHHNeTo5+Cxb6R6K6gM35mU397DuXlyTRqJoRAD+hw7avZ/kR8wkIUKMk9R?= =?us-ascii?Q?2cfko2VEhPEQbgjwxmPvteSr4mZmHZt+VFFhW+nMj3qO6iLEzLVyNs+WdCBL?= =?us-ascii?Q?Lu0l8X7dexoGzQ8d2OdOb7wXptgl6XrU4JSzFm/u98NrAb2F7p6nGrA5+CHS?= =?us-ascii?Q?paWTpfOlrXUeVnUnhcHaiZS1h52xY9+dsPhOeFfVe9A8XWvr6dMuG0OCBTY/?= =?us-ascii?Q?NhrTxucZRBIduQ1Y5vyHzjlWH2ZsM+gYo2jG97vqRRrKJc3f3AKxPCwNB+np?= =?us-ascii?Q?TivZ4oOYbA5F9d2SL7RgU3XR4kCncyNRoyOuziTYnIA5MgP85n0MZtRfzkhS?= =?us-ascii?Q?8HpTr13k1E423TPUyZMhvx+Y7lHDgL3aHhPHQF+GMEPT3nhz4luODKcubX/f?= =?us-ascii?Q?sgXB0PZD9vTsSlrdNn0Y34vtse0ZddyQjw5dOribLu0IrbAlHuFJwEFPiK6Y?= =?us-ascii?Q?XghLJq9qhwszoPYIrZ5HjH+OuiXmGYGRExgx5xQlFNnFB5+acpXrWvfHIkTs?= =?us-ascii?Q?+Rgk4UjafINzt1EG+u03xx8fHWHWyetSRhK1Ok81x/0inWkpvD2yv+eOmog3?= =?us-ascii?Q?rxIJMyU/2Fc9T3Kau1WoppYWdVaSujjYXKip7x6xbvZ8E4Vdmjl4RVir3l0f?= =?us-ascii?Q?E3GfCdVFSQp5KX0OKZLHrXw7dLVto7Plms3BH/uq+aDF087Pg6GfXvPOzJwJ?= =?us-ascii?Q?cuh9GqnCjLHrQIRKDseJVzGEznly2reCy50izaFwTzMZ+VyaKB/3MaCEXaHZ?= =?us-ascii?Q?L1+crtfVLV8/Lm+LzbQexPDwD32tvUHZer1wc3TLYm6E9e6KaFgeL96STN7b?= =?us-ascii?Q?9sLyxE0pSdBWB+oC8kAeMpUG2yuGUTzYNmyHm93Zz6N4qb9DrI8m21+O7XCT?= =?us-ascii?Q?wmBexvtGsUftspWlOZs+JxoLGKjXWcTbZNq/wfBmS+6kPlCMm8BYEk0LSw0E?= =?us-ascii?Q?g6F+7LKvXDBjEUUJpx143tuNcJP4DqMFqSNfz+n+UB0GChLLQp9bqRsBgqVI?= =?us-ascii?Q?HZ6D6j/O3dtEj02wRlvzW7y3r3ttegXt8Onep40BFZkojGZoi6ycgu41IpAe?= =?us-ascii?Q?Zuogo4EuRZS0vsMCa1YaFTYKR9RIwhL5zZhI9hPk57J2uQ1aiJLqvGAoq+D7?= =?us-ascii?Q?7pNc2lWwlJppthjVCh2gir4fnouBzbu/p6NR16fi19tuatPWzln3KDQMLQXh?= =?us-ascii?Q?9ngM8ZKwSapYEzSyI2AEk3EHm6f3noysoXWr2vf7EHbx/J6Kuodj1I+Hg9IY?= =?us-ascii?Q?yHhS9Pok+ect08NVBHH7EZabjV+1RHud+sWzec6T6qQL5BUDt0pE2+tRNo3z?= =?us-ascii?Q?5Zed0UQypExHnoQWfjfxDXAO/P0h+F4M3nVE5rr2GO6t9Eg53BKqRD/bYNuk?= =?us-ascii?Q?LxdYuwQijlLBhr1q8jYbCXYBVHC3x4jy6DQZxXFEjmU3wWcU4OiNSizVruhw?= =?us-ascii?Q?ANkNFTW7Ho+yjQuf3ZkwqFPWPNyJGy3gwV/b?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 06:29:02.9389 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52831330-b224-4c97-a279-08dd98f9f201 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6418 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jianbo Liu Previously, a unique tunnel id was added for the matching on TC non-zero chains, to support inner header rewrite with goto action. Later, it was used to support VF tunnel offload for vxlan, then for Geneve and GRE. To support VF tunnel, a temporary mlx5_flow_spec is used to parse tunnel options. For Geneve, if there is TLV option, a object is created, or refcnt is added if already exists. But the temporary mlx5_flow_spec is directly freed after parsing, which causes the leak because no information regarding the object is saved in flow's mlx5_flow_spec, which is used to free the object when deleting the flow. To fix the leak, call mlx5_geneve_tlv_option_del() before free the temporary spec if it has TLV object. Fixes: 521933cdc4aa ("net/mlx5e: Support Geneve and GRE with VF tunnel offl= oad") Signed-off-by: Jianbo Liu Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_tc.c index f1d908f61134..b9c1d7f8f05c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c @@ -2028,9 +2028,8 @@ mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv, return err; } =20 -static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow) +static bool mlx5_flow_has_geneve_opt(struct mlx5_flow_spec *spec) { - struct mlx5_flow_spec *spec =3D &flow->attr->parse_attr->spec; void *headers_v =3D MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_3); @@ -2069,7 +2068,7 @@ static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *= priv, } complete_all(&flow->del_hw_done); =20 - if (mlx5_flow_has_geneve_opt(flow)) + if (mlx5_flow_has_geneve_opt(&attr->parse_attr->spec)) mlx5_geneve_tlv_option_del(priv->mdev->geneve); =20 if (flow->decap_route) @@ -2580,6 +2579,8 @@ static int parse_tunnel_attr(struct mlx5e_priv *priv, return err; } err =3D mlx5e_tc_set_attr_rx_tun(flow, tmp_spec); + if (mlx5_flow_has_geneve_opt(tmp_spec)) + mlx5_geneve_tlv_option_del(priv->mdev->geneve); kvfree(tmp_spec); if (err) return err; --=20 2.31.1