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Tue, 20 May 2025 11:47:14 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch , Vlad Dogaru , Yevgeny Kliteynik , Gal Pressman Subject: [PATCH net-next 4/4] net/mlx5: HWS, handle modify header actions dependency Date: Tue, 20 May 2025 21:46:42 +0300 Message-ID: <1747766802-958178-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1747766802-958178-1-git-send-email-tariqt@nvidia.com> References: <1747766802-958178-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022574:EE_|DS7PR12MB9044:EE_ X-MS-Office365-Filtering-Correlation-Id: 958b6a6a-e0c3-4591-ce9e-08dd97ced0e6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?AOCzmUjj3VICkEa6ziX8erOi8fDa6DAuWLHJbm8IZAAiIUP0fmKpCnu74OCb?= =?us-ascii?Q?Xub7L/2kxKrIuPonTk+5/x/4Vt3e7MbJqUxoXTG6xz7XR4Dy+A8+hKZHVpwu?= =?us-ascii?Q?0z61gWVSbYVzk6KPFQjN+q20WEn2DpES1Ntk7d2mOEnC2R+70m06NUJQpdwK?= =?us-ascii?Q?ZM8USENPs9FIMXiXFPoLJqCgjd54MWw0o0S84fEHx58FvHun2t5YQ+n4H1D3?= =?us-ascii?Q?3JMQJXLlv7HWMcTmZBRsjcCBhU5TWZpFICZVNA+CA0nrS8BLXACpnrzxAUkv?= =?us-ascii?Q?ufU7wPAITEHaAOYVhy25/2BlAqdUG+IzsOQ/io9ulckRcG2B/YDn8xhnycc+?= =?us-ascii?Q?Cm0zDahJtCVROrgzpYvX6wuRNL6CkvX6xTOJD6jElsXdvd+KFthA8soW8OnF?= =?us-ascii?Q?xQWL9mxnMXEVKHxbN44nqGONZAvpXRUNCFJAi1qbHGAsNb450lFa8kx7jqgY?= =?us-ascii?Q?2848Z3lgwaFyeW5OQLzujWVpFbSyZKl0UHMzv2oeoIbHgHJbxRvxQptZQxLB?= =?us-ascii?Q?46nWkkPg2N9GubTYFkMwBz5tzA4hV0dZxOfkAqtwnxLsqjVEXjUA0wVyqVo7?= =?us-ascii?Q?+OzvBeBdafWvRaM76w1Es2Q93CrXVPAGzVyZw/NfajIudaOcQSzFJQxhjoJs?= =?us-ascii?Q?MxWobqB1D0iF492sA7NIXgZVYU1WD/WRg9JsY8c9lizSfytmkyysFzoiPLxF?= =?us-ascii?Q?pp8Tjue7LmlxXeHnkIiTtCaUl2EHdsvfqfQo/keiHM75a8d6H486wb0CJCkL?= =?us-ascii?Q?l34/gQMtBTNNOZHQyrGUKg+jbnPcJQvPyFRRmzSePOVHLNSlsjnocjiYkT0z?= =?us-ascii?Q?W5WJPQ/zGi8894sGekpISe0uxlcA7y4zJSmHJXk5l3pQkuqfQP02wx6xY1Ax?= =?us-ascii?Q?wN48SpAQyxnfrv46eX4you32Py+MrU6cIRXuUIzXS32VzIC3RlUuy1ZihKdW?= =?us-ascii?Q?qyxM0lL3Yz1JJ+GetAXYabVajh1IL9NNjGdbmVi1Sa0830ZAYLVWPV+OTBez?= =?us-ascii?Q?54svZmNn5hO6aKt10aLeYOfl8LOpgRzRAtMcz7vA+AGxOES6WShHfbmQmTbV?= =?us-ascii?Q?DVYcDyG5uPW+VFPYy2kf/KLHHuFTyx63DxNqXNfJPbUa56lr1AhyNx6C66Ml?= =?us-ascii?Q?KGTvEPKtutJTFvPwPkRkY29i44+xrsrunl4nde4AUjRfU8mF/qz75Gck8c9G?= =?us-ascii?Q?AQ2R1sET0NJs5axtebESdL6uW+2JS9AnuVsm+PYPeYtQ8JlqdBTggFAZ/VA6?= =?us-ascii?Q?cEdw17uXPfovNxY/KYiwdsaV68PnjExVxKnLtu82BxEQxnKt1p9IdwyDegG1?= =?us-ascii?Q?Jk9vRfwmmvLpHWeaEKfonfShKezr7+p6/WBxZdkF64Jy+IKWhhFSLYboNPCG?= =?us-ascii?Q?dkl3FNM5UvqfZag+f9ItthyhdjKrSvaqRvGiATp4bLSnHx3ZM3Nwb9Cajpo/?= =?us-ascii?Q?qDiCJGitFYERaQO/VHviI96ZP1rcoikCM0+9Fuu6dKbDtrU2ihKrgWEdHyVI?= =?us-ascii?Q?1yMM3jZgfNVACu0AxSG2FjEYV3a8DAoJ2woJ?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2025 18:47:47.8409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 958b6a6a-e0c3-4591-ce9e-08dd97ced0e6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022574.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB9044 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yevgeny Kliteynik Having adjacent accelerated modify header actions (so-called pattern-argument actions) may result in inconsistent outcome. These inconsistencies can take the form of writes to the same field or a read coupled with a write to the same field. The solution is to detect such dependencies and insert nops between the offending actions. The existing implementation had a few issues, which pretty much required a complete rewrite of the code that handles these dependencies. In the new implementation we're doing the following: * Checking any two adjacent actions for conflicts (not just odd-even pairs). * Marking 'set' and 'add' action fields as destination, rather than source, for the purposes of checking for conflicts. * Checking all types of actions ('add', 'set', 'copy') for dependencies. * Managing offsets of the args in the buffer - copy the action args to the right place in the buffer. * Checking that after inserting nops we're still within the number of supported actions - return an error otherwise. Signed-off-by: Vlad Dogaru Signed-off-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/action.c | 21 ++++-- .../mellanox/mlx5/core/steering/hws/pat_arg.c | 74 ++++++++++--------- .../mellanox/mlx5/core/steering/hws/pat_arg.h | 6 +- 3 files changed, 55 insertions(+), 46 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c = b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c index 64d115feef2c..fb62f3bc4bd4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c @@ -1190,14 +1190,15 @@ hws_action_create_modify_header_hws(struct mlx5hws_= action *action, struct mlx5hws_action_mh_pattern *pattern, u32 log_bulk_size) { + u16 num_actions, max_mh_actions =3D 0, hw_max_actions; struct mlx5hws_context *ctx =3D action->ctx; - u16 num_actions, max_mh_actions =3D 0; int i, ret, size_in_bytes; u32 pat_id, arg_id =3D 0; __be64 *new_pattern; size_t pat_max_sz; =20 pat_max_sz =3D MLX5HWS_ARG_CHUNK_SIZE_MAX * MLX5HWS_ARG_DATA_SIZE; + hw_max_actions =3D pat_max_sz / MLX5HWS_MODIFY_ACTION_SIZE; size_in_bytes =3D pat_max_sz * sizeof(__be64); new_pattern =3D kcalloc(num_of_patterns, size_in_bytes, GFP_KERNEL); if (!new_pattern) @@ -1211,10 +1212,14 @@ hws_action_create_modify_header_hws(struct mlx5hws_= action *action, =20 cur_num_actions =3D pattern[i].sz / MLX5HWS_MODIFY_ACTION_SIZE; =20 - mlx5hws_pat_calc_nop(pattern[i].data, cur_num_actions, - pat_max_sz / MLX5HWS_MODIFY_ACTION_SIZE, - &new_num_actions, &nop_locations, - &new_pattern[i * pat_max_sz]); + ret =3D mlx5hws_pat_calc_nop(pattern[i].data, cur_num_actions, + hw_max_actions, &new_num_actions, + &nop_locations, + &new_pattern[i * pat_max_sz]); + if (ret) { + mlx5hws_err(ctx, "Too many actions after nop insertion\n"); + goto free_new_pat; + } =20 action[i].modify_header.nop_locations =3D nop_locations; action[i].modify_header.num_of_actions =3D new_num_actions; @@ -2116,10 +2121,12 @@ static void hws_action_modify_write(struct mlx5hws_= send_engine *queue, if (unlikely(!new_arg_data)) return; =20 - for (i =3D 0, j =3D 0; i < num_of_actions; i++, j++) { - memcpy(&new_arg_data[j], arg_data, MLX5HWS_MODIFY_ACTION_SIZE); + for (i =3D 0, j =3D 0; j < num_of_actions; i++, j++) { if (BIT(i) & nop_locations) j++; + memcpy(&new_arg_data[j * MLX5HWS_MODIFY_ACTION_SIZE], + &arg_data[i * MLX5HWS_MODIFY_ACTION_SIZE], + MLX5HWS_MODIFY_ACTION_SIZE); } } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c index 78de19c074a7..51e4c551e0ef 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c @@ -490,8 +490,8 @@ hws_action_modify_get_target_fields(u8 action_type, __b= e64 *pattern, switch (action_type) { case MLX5_ACTION_TYPE_SET: case MLX5_ACTION_TYPE_ADD: - *src_field =3D MLX5_GET(set_action_in, pattern, field); - *dst_field =3D INVALID_FIELD; + *src_field =3D INVALID_FIELD; + *dst_field =3D MLX5_GET(set_action_in, pattern, field); break; case MLX5_ACTION_TYPE_COPY: *src_field =3D MLX5_GET(copy_action_in, pattern, src_field); @@ -522,57 +522,59 @@ bool mlx5hws_pat_verify_actions(struct mlx5hws_contex= t *ctx, __be64 pattern[], s return true; } =20 -void mlx5hws_pat_calc_nop(__be64 *pattern, size_t num_actions, - size_t max_actions, size_t *new_size, - u32 *nop_locations, __be64 *new_pat) +int mlx5hws_pat_calc_nop(__be64 *pattern, size_t num_actions, + size_t max_actions, size_t *new_size, + u32 *nop_locations, __be64 *new_pat) { - u16 prev_src_field =3D 0, prev_dst_field =3D 0; + u16 prev_src_field =3D INVALID_FIELD, prev_dst_field =3D INVALID_FIELD; u16 src_field, dst_field; u8 action_type; + bool dependent; size_t i, j; =20 *new_size =3D num_actions; *nop_locations =3D 0; =20 if (num_actions =3D=3D 1) - return; + return 0; =20 for (i =3D 0, j =3D 0; i < num_actions; i++, j++) { - action_type =3D MLX5_GET(set_action_in, &pattern[i], action_type); + if (j >=3D max_actions) + return -EINVAL; =20 + action_type =3D MLX5_GET(set_action_in, &pattern[i], action_type); hws_action_modify_get_target_fields(action_type, &pattern[i], &src_field, &dst_field); - if (i % 2) { - if (action_type =3D=3D MLX5_ACTION_TYPE_COPY && - (prev_src_field =3D=3D src_field || - prev_dst_field =3D=3D dst_field)) { - /* need Nop */ - *new_size +=3D 1; - *nop_locations |=3D BIT(i); - memset(&new_pat[j], 0, MLX5HWS_MODIFY_ACTION_SIZE); - MLX5_SET(set_action_in, &new_pat[j], - action_type, - MLX5_MODIFICATION_TYPE_NOP); - j++; - } else if (prev_src_field =3D=3D src_field) { - /* need Nop */ - *new_size +=3D 1; - *nop_locations |=3D BIT(i); - MLX5_SET(set_action_in, &new_pat[j], - action_type, - MLX5_MODIFICATION_TYPE_NOP); - j++; - } - } - memcpy(&new_pat[j], &pattern[i], MLX5HWS_MODIFY_ACTION_SIZE); - /* check if no more space */ - if (j > max_actions) { - *new_size =3D num_actions; - *nop_locations =3D 0; - return; + + /* For every action, look at it and the previous one. The two + * actions are dependent if: + */ + dependent =3D + (i > 0) && + /* At least one of the actions is a write and */ + (dst_field !=3D INVALID_FIELD || + prev_dst_field !=3D INVALID_FIELD) && + /* One reads from the other's source */ + (dst_field =3D=3D prev_src_field || + src_field =3D=3D prev_dst_field || + /* Or both write to the same destination */ + dst_field =3D=3D prev_dst_field); + + if (dependent) { + *new_size +=3D 1; + *nop_locations |=3D BIT(i); + memset(&new_pat[j], 0, MLX5HWS_MODIFY_ACTION_SIZE); + MLX5_SET(set_action_in, &new_pat[j], action_type, + MLX5_MODIFICATION_TYPE_NOP); + j++; + if (j >=3D max_actions) + return -EINVAL; } =20 + memcpy(&new_pat[j], &pattern[i], MLX5HWS_MODIFY_ACTION_SIZE); prev_src_field =3D src_field; prev_dst_field =3D dst_field; } + + return 0; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h index 91bd2572a341..7fbd8dc7aa18 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h @@ -96,7 +96,7 @@ int mlx5hws_arg_write_inline_arg_data(struct mlx5hws_cont= ext *ctx, u8 *arg_data, size_t data_size); =20 -void mlx5hws_pat_calc_nop(__be64 *pattern, size_t num_actions, - size_t max_actions, size_t *new_size, - u32 *nop_locations, __be64 *new_pat); +int mlx5hws_pat_calc_nop(__be64 *pattern, size_t num_actions, + size_t max_actions, size_t *new_size, + u32 *nop_locations, __be64 *new_pat); #endif /* MLX5HWS_PAT_ARG_H_ */ --=20 2.31.1