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Tue, 20 May 2025 11:47:02 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch , Vlad Dogaru , Yevgeny Kliteynik , Gal Pressman Subject: [PATCH net-next 1/4] net/mlx5: SWS, fix reformat id error handling Date: Tue, 20 May 2025 21:46:39 +0300 Message-ID: <1747766802-958178-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1747766802-958178-1-git-send-email-tariqt@nvidia.com> References: <1747766802-958178-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FA:EE_|CY8PR12MB8066:EE_ X-MS-Office365-Filtering-Correlation-Id: cb25d138-92b3-4753-f34d-08dd97cec30b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?q2YEW+BBOLXLBIeAJbT2UiIU0A9zjBEOXpKIYTEL1731WwcnOHENcs/IKIRI?= =?us-ascii?Q?9OzsHqMIyOh9sPhXgVyys9z+Kxw1gZVsNvWIqfIX4Pj+gxKeRdEOEOmaHNtH?= =?us-ascii?Q?iRRsV950nuw3RulmOVbiwDbUn76XEFra01+ufNAsFQZU7BhLMlfEhxxVlIwh?= =?us-ascii?Q?4ds/SqtH11cgBe4K4vbaIF6KRPxlLaxnGWS3bB9MOBSPAlMn1+F/s5Fc7Mpj?= =?us-ascii?Q?Ek6mVkC6APlDRZ3UDz8MT3aJbb35lI5GfzbjdMKOwQDgarChIeW7V0Obws5G?= =?us-ascii?Q?jrWkSHFcU+RFDCp9grbWVeWKjBiiMfxtLtqg6QCPj8E6GIyBNIPMJhvVlt24?= =?us-ascii?Q?YHTn+Bv8t8vZzoJ6FxLn5ZVC7tLcRgrKat2bTXTKJ6PWo5/8/OpXsO+KQZRA?= =?us-ascii?Q?/NRf8uZoNpE6HKHHoNrwNcACjzX5EZdwJrEbhBV4mkZZhXuO+yCgNR85OSf7?= =?us-ascii?Q?Ntn5mtmbtkearcXB9N2/WURMrAcScC23rejSO/jrBnQ0PMn+qdQ31wr/vaRm?= =?us-ascii?Q?Y3srNEjE2pq1b8uZXrCBTcXLKmmjRN0E8dLw6Az5lJOiuuurw8LH1logqgFO?= =?us-ascii?Q?U3KdgxipZtue5PKZuvpfejnEHUyiFrOjgMLrhO5lmeronMCYbvqZCddZf7gx?= =?us-ascii?Q?+GOiF2aCMGpFucCXEaGNZI8n8/4ihBibhfkZMFqhTsXZ9qAdF2NrjO9yf4A4?= =?us-ascii?Q?NH5p7QhdKKKHUehI5mczcpUAx5+RBtuuGb/nBR9NvhP9PXEdCIYEg+gQ+oOn?= =?us-ascii?Q?WKADQPm80iqsvQI/9v9yA77RUu2FireAfrfTx6wueqny7MDTy9XGktMRuOkR?= =?us-ascii?Q?dw7USyIYq2TWVhl3qsh+ka684gQidHm+vk+RCr+BjI/nOJz/dfHd5breA8Hy?= =?us-ascii?Q?gM7+KBLaPYvENYELOObq3xgIJR6ji7awYF9gg/72OGkfE61Yy7s1JPXOfDAa?= =?us-ascii?Q?wtNuaWHa0xSsmfYWrc96UdajmFhfMn7RS/Hf+WaaiX4PW2f1fMoKrFbtIbzA?= =?us-ascii?Q?oDXUH/11a4H+OjYW6U4UMRnpStTDPdStptMM+mu6nU3pbquoFZ985/uE5/Xr?= =?us-ascii?Q?uFVa/RY9MYs4Xbvp03mqgXSD+zR9HY5vzbPxYW5J0YiDihwezEvAwwhLqaQV?= =?us-ascii?Q?Fuw/KewIwE2HQc+eFMJoVXmlxio/jR0tAQyzUnhfXTQDeKQAhwumyCv/7MDE?= =?us-ascii?Q?Cxl/9IdHiEwXma3CYyvx4kDKcYGaNvbaLH6bCfZaWKPLPJDME2l/FwamcXs2?= =?us-ascii?Q?yTOKBbmduq5B9TdqWvZhubZ2Ct9YQsY/wphwhfN9kJNpb8ix3bkFf9QAazx9?= =?us-ascii?Q?1SIBDR+H6ql3Br4dlNEd4eMnD4D2XWAN40AUVzx+8X+3c900HaLhywlY/NOB?= =?us-ascii?Q?KV7wB828Z5N6M8keTu1E8xQ9as4XS6ETv3esw04o5HqgPCXZ3oB+E1Ln3NGa?= =?us-ascii?Q?1lKqc933r4bG+gouBQRtOjl0oyAgehbDFRSNc7BAd8KIpfcVmbVL1petMA6T?= =?us-ascii?Q?7Dis9vSFECsvkVWGqC/83Py/Wi+BPVhQaUNA?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2025 18:47:24.6064 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb25d138-92b3-4753-f34d-08dd97cec30b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8066 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Vlad Dogaru The firmware reformat id is a u32 and can't safely be returned as an int. Because the functions also need a way to signal error, prefer to return the id as an output parameter and keep the return code only for success/error. While we're at it, also extract some duplicate code to fetch the reformat id from a more generic struct pkt_reformat. Signed-off-by: Vlad Dogaru Signed-off-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/fs_cmd.c | 28 +++++++++--------- .../net/ethernet/mellanox/mlx5/core/fs_core.c | 29 +++++++++++++++---- .../net/ethernet/mellanox/mlx5/core/fs_core.h | 3 ++ .../mellanox/mlx5/core/steering/sws/fs_dr.c | 10 +++++-- .../mellanox/mlx5/core/steering/sws/fs_dr.h | 10 +++++-- 5 files changed, 55 insertions(+), 25 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c b/drivers/net= /ethernet/mellanox/mlx5/core/fs_cmd.c index a47c29571f64..1af76da8b132 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c @@ -527,7 +527,7 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, struct mlx5_flow_rule *dst; void *in_flow_context, *vlan; void *in_match_value; - int reformat_id =3D 0; + u32 reformat_id =3D 0; unsigned int inlen; int dst_cnt_size; u32 *in, action; @@ -580,23 +580,21 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, MLX5_SET(flow_context, in_flow_context, action, action); =20 if (!extended_dest && fte->act_dests.action.pkt_reformat) { - struct mlx5_pkt_reformat *pkt_reformat =3D fte->act_dests.action.pkt_ref= ormat; - - if (pkt_reformat->owner =3D=3D MLX5_FLOW_RESOURCE_OWNER_SW) { - reformat_id =3D mlx5_fs_dr_action_get_pkt_reformat_id(pkt_reformat); - if (reformat_id < 0) { - mlx5_core_err(dev, - "Unsupported SW-owned pkt_reformat type (%d) in FW-owned table\= n", - pkt_reformat->reformat_type); - err =3D reformat_id; - goto err_out; - } - } else { - reformat_id =3D fte->act_dests.action.pkt_reformat->id; + struct mlx5_pkt_reformat *pkt_reformat =3D + fte->act_dests.action.pkt_reformat; + + err =3D mlx5_fs_get_packet_reformat_id(pkt_reformat, + &reformat_id); + if (err) { + mlx5_core_err(dev, + "Unsupported pkt_reformat type (%d)\n", + pkt_reformat->reformat_type); + goto err_out; } } =20 - MLX5_SET(flow_context, in_flow_context, packet_reformat_id, (u32)reformat= _id); + MLX5_SET(flow_context, in_flow_context, packet_reformat_id, + reformat_id); =20 if (fte->act_dests.action.modify_hdr) { if (fte->act_dests.action.modify_hdr->owner =3D=3D MLX5_FLOW_RESOURCE_OW= NER_SW) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.c index 6163bc98d94a..a81b81a3b8f0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -1830,14 +1830,33 @@ static int create_auto_flow_group(struct mlx5_flow_= table *ft, return err; } =20 +int mlx5_fs_get_packet_reformat_id(struct mlx5_pkt_reformat *pkt_reformat, + u32 *id) +{ + switch (pkt_reformat->owner) { + case MLX5_FLOW_RESOURCE_OWNER_FW: + *id =3D pkt_reformat->id; + return 0; + case MLX5_FLOW_RESOURCE_OWNER_SW: + return mlx5_fs_dr_action_get_pkt_reformat_id(pkt_reformat, id); + default: + return -EINVAL; + } +} + static bool mlx5_pkt_reformat_cmp(struct mlx5_pkt_reformat *p1, struct mlx5_pkt_reformat *p2) { - return p1->owner =3D=3D p2->owner && - (p1->owner =3D=3D MLX5_FLOW_RESOURCE_OWNER_FW ? - p1->id =3D=3D p2->id : - mlx5_fs_dr_action_get_pkt_reformat_id(p1) =3D=3D - mlx5_fs_dr_action_get_pkt_reformat_id(p2)); + int err1, err2; + u32 id1, id2; + + if (p1->owner !=3D p2->owner) + return false; + + err1 =3D mlx5_fs_get_packet_reformat_id(p1, &id1); + err2 =3D mlx5_fs_get_packet_reformat_id(p2, &id2); + + return !err1 && !err2 && id1 =3D=3D id2; } =20 static bool mlx5_flow_dests_cmp(struct mlx5_flow_destination *d1, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.h index 0767239f651c..248a74108fb1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h @@ -386,6 +386,9 @@ u32 mlx5_fs_get_capabilities(struct mlx5_core_dev *dev,= enum mlx5_flow_namespace =20 struct mlx5_flow_root_namespace *find_root(struct fs_node *node); =20 +int mlx5_fs_get_packet_reformat_id(struct mlx5_pkt_reformat *pkt_reformat, + u32 *id); + #define fs_get_obj(v, _node) {v =3D container_of((_node), typeof(*v), nod= e); } =20 #define fs_list_for_each_entry(pos, root) \ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/fs_dr.c b= /drivers/net/ethernet/mellanox/mlx5/core/steering/sws/fs_dr.c index 8007d3f523c9..f367997ab61e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/fs_dr.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/fs_dr.c @@ -833,15 +833,21 @@ static u32 mlx5_cmd_dr_get_capabilities(struct mlx5_f= low_root_namespace *ns, return steering_caps; } =20 -int mlx5_fs_dr_action_get_pkt_reformat_id(struct mlx5_pkt_reformat *pkt_re= format) +int +mlx5_fs_dr_action_get_pkt_reformat_id(struct mlx5_pkt_reformat *pkt_reform= at, + u32 *reformat_id) { + struct mlx5dr_action *dr_action; + switch (pkt_reformat->reformat_type) { case MLX5_REFORMAT_TYPE_L2_TO_VXLAN: case MLX5_REFORMAT_TYPE_L2_TO_NVGRE: case MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL: case MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL: case MLX5_REFORMAT_TYPE_INSERT_HDR: - return mlx5dr_action_get_pkt_reformat_id(pkt_reformat->fs_dr_action.dr_a= ction); + dr_action =3D pkt_reformat->fs_dr_action.dr_action; + *reformat_id =3D mlx5dr_action_get_pkt_reformat_id(dr_action); + return 0; } return -EOPNOTSUPP; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/fs_dr.h b= /drivers/net/ethernet/mellanox/mlx5/core/steering/sws/fs_dr.h index 99a3b2eff6b8..f869f2daefbf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/fs_dr.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/fs_dr.h @@ -38,7 +38,9 @@ struct mlx5_fs_dr_table { =20 bool mlx5_fs_dr_is_supported(struct mlx5_core_dev *dev); =20 -int mlx5_fs_dr_action_get_pkt_reformat_id(struct mlx5_pkt_reformat *pkt_re= format); +int +mlx5_fs_dr_action_get_pkt_reformat_id(struct mlx5_pkt_reformat *pkt_reform= at, + u32 *reformat_id); =20 const struct mlx5_flow_cmds *mlx5_fs_cmd_get_dr_cmds(void); =20 @@ -49,9 +51,11 @@ static inline const struct mlx5_flow_cmds *mlx5_fs_cmd_g= et_dr_cmds(void) return NULL; } =20 -static inline u32 mlx5_fs_dr_action_get_pkt_reformat_id(struct mlx5_pkt_re= format *pkt_reformat) +static inline int +mlx5_fs_dr_action_get_pkt_reformat_id(struct mlx5_pkt_reformat *pkt_reform= at, + u32 *reformat_id) { - return 0; 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Tue, 20 May 2025 11:47:06 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch , Vlad Dogaru , Yevgeny Kliteynik , Gal Pressman Subject: [PATCH net-next 2/4] net/mlx5: HWS, register reformat actions with fw Date: Tue, 20 May 2025 21:46:40 +0300 Message-ID: <1747766802-958178-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1747766802-958178-1-git-send-email-tariqt@nvidia.com> References: <1747766802-958178-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FA:EE_|BN7PPF3C1137D8A:EE_ X-MS-Office365-Filtering-Correlation-Id: 40b8cff2-1b36-405c-190d-08dd97cec576 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?1idv8MVPmIE4jFxrvLTENKinNx4WXQyS1k0j/uYDnolDtY6DN3D2Z0QD5dAC?= =?us-ascii?Q?QFWnRcDpqORJu/i1iiQ20+iNhZ17Cly3gpZtFSDpLgb1Z6Fmt3HlnYhEAHR7?= =?us-ascii?Q?Q924j+METtF2+gaT4cx+z2vOW/BhFuh26rovbV3UNJNjfKw4PJVGitu7kXlm?= =?us-ascii?Q?udL7p64d2ryDl6bktRmiaqJ1SZI161ArugDUqpobVoWPgQ6iWsLLVXCw2Pxt?= =?us-ascii?Q?4gI1O0W8EOoi77KCZfMAJszJqctV4KRUK2wrtyTwHgiYACuKkP/RlW2gFt8n?= =?us-ascii?Q?wRyopVJL7a2KLySGY5BXR9/gH1Au5X3GUHosVrEhaV+z7XsOBkZEjlAmSnZm?= =?us-ascii?Q?OXCCDBDx6aUuiwdvrkAaRcj9lMH0dgSSm7VofUUfatj+2VKx+M3RIqYP7ETv?= =?us-ascii?Q?mBmxmADxBb1pa5trGUMMn0pG9R3IGe/546B/GhTa9GfM7dV2zZKVbdkqVP6T?= =?us-ascii?Q?YN+qXAq2St6zwfYbIo9lqv2uNyfgMC5BvCirP0CFdZkVbTOAJtLb7XDWVsYw?= =?us-ascii?Q?2Y2udrXd8HWTRbVLRsyPntWwdR3Rm9znhUMCmqz8bYzsJHYqV10XS5+3+veg?= =?us-ascii?Q?zdl4qZaw6hUYK91OQ4cEfEe+N5b/Dd6hJT5/r6+ydw3+ggQfebZRaZqzKraT?= =?us-ascii?Q?0Fz+NSrsFs/5E5r4JIV1bX3tRRSZTnuYkCvcgCiBaxfL5Q6frzOPCulUTnH6?= =?us-ascii?Q?rS3XTICUVMoTpF4CNvdSFCwpjnNRqANV1jcylRgt6eGwyYs7om9/lilo4noE?= =?us-ascii?Q?K41RGxEGjS7djcDs2c7vIhvK1G/2MIhHS62FeRDmwdz3pLlS5w76hy/LgGAX?= =?us-ascii?Q?+Az3Nm5lmRioG4Upwn033pxn6IZbTlaTNyGwCLjtUX1UHAUnscQ+ffX9MUTU?= =?us-ascii?Q?iq/D3zMLIqbDzlFqQhx0oQS6FaihyBNafQ4Dvl1rgnrfWo4v3QTxYZm1fqff?= =?us-ascii?Q?eYV1w5vOJsCGQUw1oVn025dK2EWv6cAUrSAJcq4FBAgmX29g7LkwqFfVYZ6i?= =?us-ascii?Q?9AAftGAf1yzdB0AGos15RGVADDk9K2Vc0eNSqt7UaRfqN3JI8krAUN9lo/TX?= =?us-ascii?Q?S2uuRHuysbIW1PcMMulbl2s0Guu0VN6LyUmYcOaOEeWqoI8F8sZ9Zu3TN5NV?= =?us-ascii?Q?j5zQCebHEz1F7s7Y7A3vLrDOtIhpIYLIPNgIQynzR7zG0G2vFEozpwJB7vLR?= =?us-ascii?Q?QCPGg4oaJybrPsFHHZhK53PeOhIXWSWzvZ0FU3R9BTJ/d4db29cD00UipDMf?= =?us-ascii?Q?rz8mmGhuXbWN9US9xKvBi7vdT0+uCwGFQTTUrBaHSX8F+/YKH41A0pT3cN4h?= =?us-ascii?Q?SL9e1vFqXsWcWaFGBMGUcK5GkLXS1dGYPe0Mjdr8vSVQ9WEy+iUlwhlbHsiO?= =?us-ascii?Q?aOwlSoidqr4J4xxL/v2cvLgr9BEZ8S2t9UX/6CgI0UiinbhfXkpIysEOaz86?= =?us-ascii?Q?z0m3SmvayqB6GWIYPVYZwvdvkCAHY26LADdbp/NDTcsH1vqsnuey/MoFOifG?= =?us-ascii?Q?6+/O31Qw3A2HAFEo4cZaIrr7QfBplW1IgwDh?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2025 18:47:28.7003 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40b8cff2-1b36-405c-190d-08dd97cec576 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF3C1137D8A Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Vlad Dogaru Hardware steering handles actions differently from firmware, but for termination rules that use encapsulation the firmware needs to be aware of the action. Fix this by registering reformat actions with the firmware the first time this is needed. To do this, add a third possible owner for an action, and also a lock to protect against registration of the same action from different threads. Signed-off-by: Vlad Dogaru Signed-off-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/fs_core.c | 2 + .../net/ethernet/mellanox/mlx5/core/fs_core.h | 1 + .../mellanox/mlx5/core/steering/hws/action.c | 5 ++ .../mellanox/mlx5/core/steering/hws/fs_hws.c | 71 +++++++++++++++++-- .../mellanox/mlx5/core/steering/hws/fs_hws.h | 16 +++++ .../mellanox/mlx5/core/steering/hws/mlx5hws.h | 9 +++ 6 files changed, 97 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.c index a81b81a3b8f0..23a7e8e7adfa 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -1839,6 +1839,8 @@ int mlx5_fs_get_packet_reformat_id(struct mlx5_pkt_re= format *pkt_reformat, return 0; case MLX5_FLOW_RESOURCE_OWNER_SW: return mlx5_fs_dr_action_get_pkt_reformat_id(pkt_reformat, id); + case MLX5_FLOW_RESOURCE_OWNER_HWS: + return mlx5_fs_hws_action_get_pkt_reformat_id(pkt_reformat, id); default: return -EINVAL; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.h index 248a74108fb1..500826229b0b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h @@ -58,6 +58,7 @@ struct mlx5_flow_definer { enum mlx5_flow_resource_owner { MLX5_FLOW_RESOURCE_OWNER_FW, MLX5_FLOW_RESOURCE_OWNER_SW, + MLX5_FLOW_RESOURCE_OWNER_HWS, }; =20 struct mlx5_modify_hdr { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c = b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c index bef4d25c1a2a..aa47a7af6f50 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c @@ -72,6 +72,11 @@ enum mlx5hws_action_type mlx5hws_action_get_type(struct = mlx5hws_action *action) return action->type; } =20 +struct mlx5_core_dev *mlx5hws_action_get_dev(struct mlx5hws_action *action) +{ + return action->ctx->mdev; +} + static int hws_action_get_shared_stc_nic(struct mlx5hws_context *ctx, enum mlx5hws_context_shared_stc_type stc_type, u8 tbl_type) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.c = b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.c index 1b787cd66e6f..9d1c0e4b224a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.c @@ -1081,13 +1081,8 @@ static int mlx5_cmd_hws_create_fte(struct mlx5_flow_= root_namespace *ns, struct mlx5hws_bwc_rule *rule; int err =3D 0; =20 - if (mlx5_fs_cmd_is_fw_term_table(ft)) { - /* Packet reformat on terminamtion table not supported yet */ - if (fte->act_dests.action.action & - MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) - return -EOPNOTSUPP; + if (mlx5_fs_cmd_is_fw_term_table(ft)) return mlx5_fs_cmd_get_fw_cmds()->create_fte(ns, ft, group, fte); - } =20 err =3D mlx5_fs_fte_get_hws_actions(ns, ft, group, fte, &ractions); if (err) @@ -1362,7 +1357,7 @@ mlx5_cmd_hws_packet_reformat_alloc(struct mlx5_flow_r= oot_namespace *ns, pkt_reformat->fs_hws_action.pr_data =3D pr_data; } =20 - pkt_reformat->owner =3D MLX5_FLOW_RESOURCE_OWNER_SW; + pkt_reformat->owner =3D MLX5_FLOW_RESOURCE_OWNER_HWS; pkt_reformat->fs_hws_action.hws_action =3D hws_action; return 0; =20 @@ -1380,6 +1375,15 @@ static void mlx5_cmd_hws_packet_reformat_dealloc(str= uct mlx5_flow_root_namespace struct mlx5_fs_hws_pr *pr_data; struct mlx5_fs_pool *pr_pool; =20 + if (pkt_reformat->fs_hws_action.fw_reformat_id !=3D 0) { + struct mlx5_pkt_reformat fw_pkt_reformat =3D { 0 }; + + fw_pkt_reformat.id =3D pkt_reformat->fs_hws_action.fw_reformat_id; + mlx5_fs_cmd_get_fw_cmds()-> + packet_reformat_dealloc(ns, &fw_pkt_reformat); + pkt_reformat->fs_hws_action.fw_reformat_id =3D 0; + } + if (pkt_reformat->reformat_type =3D=3D MLX5_REFORMAT_TYPE_REMOVE_HDR) return; =20 @@ -1499,6 +1503,7 @@ static int mlx5_cmd_hws_modify_header_alloc(struct ml= x5_flow_root_namespace *ns, err =3D -ENOMEM; goto release_mh; } + mutex_init(&modify_hdr->fs_hws_action.lock); modify_hdr->fs_hws_action.mh_data =3D mh_data; modify_hdr->fs_hws_action.fs_pool =3D pool; modify_hdr->owner =3D MLX5_FLOW_RESOURCE_OWNER_SW; @@ -1532,6 +1537,58 @@ static void mlx5_cmd_hws_modify_header_dealloc(struc= t mlx5_flow_root_namespace * modify_hdr->fs_hws_action.mh_data =3D NULL; } =20 +int +mlx5_fs_hws_action_get_pkt_reformat_id(struct mlx5_pkt_reformat *pkt_refor= mat, + u32 *reformat_id) +{ + enum mlx5_flow_namespace_type ns_type =3D pkt_reformat->ns_type; + struct mutex *lock =3D &pkt_reformat->fs_hws_action.lock; + u32 *id =3D &pkt_reformat->fs_hws_action.fw_reformat_id; + struct mlx5_pkt_reformat fw_pkt_reformat =3D { 0 }; + struct mlx5_pkt_reformat_params params =3D { 0 }; + struct mlx5_flow_root_namespace *ns; + struct mlx5_core_dev *dev; + int ret; + + mutex_lock(lock); + + if (*id !=3D 0) { + *reformat_id =3D *id; + ret =3D 0; + goto unlock; + } + + dev =3D mlx5hws_action_get_dev(pkt_reformat->fs_hws_action.hws_action); + if (!dev) { + ret =3D -EINVAL; + goto unlock; + } + + ns =3D mlx5_get_root_namespace(dev, ns_type); + if (!ns) { + ret =3D -EINVAL; + goto unlock; + } + + params.type =3D pkt_reformat->reformat_type; + params.size =3D pkt_reformat->fs_hws_action.pr_data->data_size; + params.data =3D pkt_reformat->fs_hws_action.pr_data->data; + + ret =3D mlx5_fs_cmd_get_fw_cmds()-> + packet_reformat_alloc(ns, ¶ms, ns_type, &fw_pkt_reformat); + if (ret) + goto unlock; + + *id =3D fw_pkt_reformat.id; + *reformat_id =3D *id; + ret =3D 0; + +unlock: + mutex_unlock(lock); + + return ret; +} + static int mlx5_cmd_hws_create_match_definer(struct mlx5_flow_root_namespa= ce *ns, u16 format_id, u32 *match_mask) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.h = b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.h index 8b56298288da..b92d55b2d147 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.h @@ -41,6 +41,11 @@ struct mlx5_fs_hws_action { struct mlx5_fs_pool *fs_pool; struct mlx5_fs_hws_pr *pr_data; struct mlx5_fs_hws_mh *mh_data; + u32 fw_reformat_id; + /* Protect `fw_reformat_id` against being initialized from multiple + * threads. + */ + struct mutex lock; }; =20 struct mlx5_fs_hws_matcher { @@ -84,12 +89,23 @@ void mlx5_fs_put_hws_action(struct mlx5_fs_hws_data *fs= _hws_data); =20 #ifdef CONFIG_MLX5_HW_STEERING =20 +int +mlx5_fs_hws_action_get_pkt_reformat_id(struct mlx5_pkt_reformat *pkt_refor= mat, + u32 *reformat_id); + bool mlx5_fs_hws_is_supported(struct mlx5_core_dev *dev); =20 const struct mlx5_flow_cmds *mlx5_fs_cmd_get_hws_cmds(void); =20 #else =20 +static inline int +mlx5_fs_hws_action_get_pkt_reformat_id(struct mlx5_pkt_reformat *pkt_refor= mat, + u32 *reformat_id) +{ + return -EOPNOTSUPP; +} + static inline bool mlx5_fs_hws_is_supported(struct mlx5_core_dev *dev) { return false; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h index fbd63369da10..9bbadc4d8a0b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h @@ -503,6 +503,15 @@ int mlx5hws_rule_action_update(struct mlx5hws_rule *ru= le, enum mlx5hws_action_type mlx5hws_action_get_type(struct mlx5hws_action *action); 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To shorten the lines, this renaming also required some refactoring. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/action.c | 53 ++++++++++--------- .../mellanox/mlx5/core/steering/hws/action.h | 2 +- .../mellanox/mlx5/core/steering/hws/pat_arg.c | 18 +++---- .../mellanox/mlx5/core/steering/hws/pat_arg.h | 5 +- 4 files changed, 41 insertions(+), 37 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c = b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c index aa47a7af6f50..64d115feef2c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c @@ -1207,16 +1207,16 @@ hws_action_create_modify_header_hws(struct mlx5hws_= action *action, for (i =3D 0; i < num_of_patterns; i++) { size_t new_num_actions; size_t cur_num_actions; - u32 nope_location; + u32 nop_locations; =20 cur_num_actions =3D pattern[i].sz / MLX5HWS_MODIFY_ACTION_SIZE; =20 - mlx5hws_pat_calc_nope(pattern[i].data, cur_num_actions, - pat_max_sz / MLX5HWS_MODIFY_ACTION_SIZE, - &new_num_actions, &nope_location, - &new_pattern[i * pat_max_sz]); + mlx5hws_pat_calc_nop(pattern[i].data, cur_num_actions, + pat_max_sz / MLX5HWS_MODIFY_ACTION_SIZE, + &new_num_actions, &nop_locations, + &new_pattern[i * pat_max_sz]); =20 - action[i].modify_header.nope_locations =3D nope_location; + action[i].modify_header.nop_locations =3D nop_locations; action[i].modify_header.num_of_actions =3D new_num_actions; =20 max_mh_actions =3D max(max_mh_actions, new_num_actions); @@ -1263,7 +1263,7 @@ hws_action_create_modify_header_hws(struct mlx5hws_ac= tion *action, MLX5_GET(set_action_in, pattern[i].data, action_type); } else { /* Multiple modify actions require a pattern */ - if (unlikely(action[i].modify_header.nope_locations)) { + if (unlikely(action[i].modify_header.nop_locations)) { size_t pattern_sz; =20 pattern_sz =3D action[i].modify_header.num_of_actions * @@ -2105,12 +2105,12 @@ static void hws_action_modify_write(struct mlx5hws_= send_engine *queue, u32 arg_idx, u8 *arg_data, u16 num_of_actions, - u32 nope_locations) + u32 nop_locations) { u8 *new_arg_data =3D NULL; int i, j; =20 - if (unlikely(nope_locations)) { + if (unlikely(nop_locations)) { new_arg_data =3D kcalloc(num_of_actions, MLX5HWS_MODIFY_ACTION_SIZE, GFP_KERNEL); if (unlikely(!new_arg_data)) @@ -2118,7 +2118,7 @@ static void hws_action_modify_write(struct mlx5hws_se= nd_engine *queue, =20 for (i =3D 0, j =3D 0; i < num_of_actions; i++, j++) { memcpy(&new_arg_data[j], arg_data, MLX5HWS_MODIFY_ACTION_SIZE); - if (BIT(i) & nope_locations) + if (BIT(i) & nop_locations) j++; } } @@ -2215,6 +2215,7 @@ hws_action_setter_modify_header(struct mlx5hws_action= s_apply_data *apply, struct mlx5hws_action *action; u32 arg_sz, arg_idx; u8 *single_action; + u8 max_actions; __be32 stc_idx; =20 rule_action =3D &apply->rule_action[setter->idx_double]; @@ -2242,21 +2243,23 @@ hws_action_setter_modify_header(struct mlx5hws_acti= ons_apply_data *apply, =20 apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW7] =3D *(__be32 *)MLX5_ADDR_OF(set_action_in, single_action, data); - } else { - /* Argument offset multiple with number of args per these actions */ - arg_sz =3D mlx5hws_arg_get_arg_size(action->modify_header.max_num_of_act= ions); - arg_idx =3D rule_action->modify_header.offset * arg_sz; - - apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW7] =3D htonl(arg_idx); - - if (!(action->flags & MLX5HWS_ACTION_FLAG_SHARED)) { - apply->require_dep =3D 1; - hws_action_modify_write(apply->queue, - action->modify_header.arg_id + arg_idx, - rule_action->modify_header.data, - action->modify_header.num_of_actions, - action->modify_header.nope_locations); - } + return; + } + + /* Argument offset multiple with number of args per these actions */ + max_actions =3D action->modify_header.max_num_of_actions; + arg_sz =3D mlx5hws_arg_get_arg_size(max_actions); + arg_idx =3D rule_action->modify_header.offset * arg_sz; + + apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW7] =3D htonl(arg_idx); + + if (!(action->flags & MLX5HWS_ACTION_FLAG_SHARED)) { + apply->require_dep =3D 1; + hws_action_modify_write(apply->queue, + action->modify_header.arg_id + arg_idx, + rule_action->modify_header.data, + action->modify_header.num_of_actions, + action->modify_header.nop_locations); } } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h = b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h index 25fa0d4c9221..55a079fdd08f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h @@ -136,7 +136,7 @@ struct mlx5hws_action { u32 pat_id; u32 arg_id; __be64 single_action; - u32 nope_locations; + u32 nop_locations; u8 num_of_patterns; u8 single_action_type; u8 num_of_actions; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c index f51ed24526b9..78de19c074a7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c @@ -522,9 +522,9 @@ bool mlx5hws_pat_verify_actions(struct mlx5hws_context = *ctx, __be64 pattern[], s return true; } =20 -void mlx5hws_pat_calc_nope(__be64 *pattern, size_t num_actions, - size_t max_actions, size_t *new_size, - u32 *nope_location, __be64 *new_pat) +void mlx5hws_pat_calc_nop(__be64 *pattern, size_t num_actions, + size_t max_actions, size_t *new_size, + u32 *nop_locations, __be64 *new_pat) { u16 prev_src_field =3D 0, prev_dst_field =3D 0; u16 src_field, dst_field; @@ -532,7 +532,7 @@ void mlx5hws_pat_calc_nope(__be64 *pattern, size_t num_= actions, size_t i, j; =20 *new_size =3D num_actions; - *nope_location =3D 0; + *nop_locations =3D 0; =20 if (num_actions =3D=3D 1) return; @@ -546,18 +546,18 @@ void mlx5hws_pat_calc_nope(__be64 *pattern, size_t nu= m_actions, if (action_type =3D=3D MLX5_ACTION_TYPE_COPY && (prev_src_field =3D=3D src_field || prev_dst_field =3D=3D dst_field)) { - /* need Nope */ + /* need Nop */ *new_size +=3D 1; - *nope_location |=3D BIT(i); + *nop_locations |=3D BIT(i); memset(&new_pat[j], 0, MLX5HWS_MODIFY_ACTION_SIZE); MLX5_SET(set_action_in, &new_pat[j], action_type, MLX5_MODIFICATION_TYPE_NOP); j++; } else if (prev_src_field =3D=3D src_field) { - /* need Nope*/ + /* need Nop */ *new_size +=3D 1; - *nope_location |=3D BIT(i); + *nop_locations |=3D BIT(i); MLX5_SET(set_action_in, &new_pat[j], action_type, MLX5_MODIFICATION_TYPE_NOP); @@ -568,7 +568,7 @@ void mlx5hws_pat_calc_nope(__be64 *pattern, size_t num_= actions, /* check if no more space */ if (j > max_actions) { *new_size =3D num_actions; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch , Vlad Dogaru , Yevgeny Kliteynik , Gal Pressman Subject: [PATCH net-next 4/4] net/mlx5: HWS, handle modify header actions dependency Date: Tue, 20 May 2025 21:46:42 +0300 Message-ID: <1747766802-958178-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1747766802-958178-1-git-send-email-tariqt@nvidia.com> References: <1747766802-958178-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022574:EE_|DS7PR12MB9044:EE_ X-MS-Office365-Filtering-Correlation-Id: 958b6a6a-e0c3-4591-ce9e-08dd97ced0e6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?AOCzmUjj3VICkEa6ziX8erOi8fDa6DAuWLHJbm8IZAAiIUP0fmKpCnu74OCb?= =?us-ascii?Q?Xub7L/2kxKrIuPonTk+5/x/4Vt3e7MbJqUxoXTG6xz7XR4Dy+A8+hKZHVpwu?= =?us-ascii?Q?0z61gWVSbYVzk6KPFQjN+q20WEn2DpES1Ntk7d2mOEnC2R+70m06NUJQpdwK?= =?us-ascii?Q?ZM8USENPs9FIMXiXFPoLJqCgjd54MWw0o0S84fEHx58FvHun2t5YQ+n4H1D3?= =?us-ascii?Q?3JMQJXLlv7HWMcTmZBRsjcCBhU5TWZpFICZVNA+CA0nrS8BLXACpnrzxAUkv?= =?us-ascii?Q?ufU7wPAITEHaAOYVhy25/2BlAqdUG+IzsOQ/io9ulckRcG2B/YDn8xhnycc+?= =?us-ascii?Q?Cm0zDahJtCVROrgzpYvX6wuRNL6CkvX6xTOJD6jElsXdvd+KFthA8soW8OnF?= =?us-ascii?Q?xQWL9mxnMXEVKHxbN44nqGONZAvpXRUNCFJAi1qbHGAsNb450lFa8kx7jqgY?= =?us-ascii?Q?2848Z3lgwaFyeW5OQLzujWVpFbSyZKl0UHMzv2oeoIbHgHJbxRvxQptZQxLB?= =?us-ascii?Q?46nWkkPg2N9GubTYFkMwBz5tzA4hV0dZxOfkAqtwnxLsqjVEXjUA0wVyqVo7?= =?us-ascii?Q?+OzvBeBdafWvRaM76w1Es2Q93CrXVPAGzVyZw/NfajIudaOcQSzFJQxhjoJs?= =?us-ascii?Q?MxWobqB1D0iF492sA7NIXgZVYU1WD/WRg9JsY8c9lizSfytmkyysFzoiPLxF?= =?us-ascii?Q?pp8Tjue7LmlxXeHnkIiTtCaUl2EHdsvfqfQo/keiHM75a8d6H486wb0CJCkL?= =?us-ascii?Q?l34/gQMtBTNNOZHQyrGUKg+jbnPcJQvPyFRRmzSePOVHLNSlsjnocjiYkT0z?= =?us-ascii?Q?W5WJPQ/zGi8894sGekpISe0uxlcA7y4zJSmHJXk5l3pQkuqfQP02wx6xY1Ax?= =?us-ascii?Q?wN48SpAQyxnfrv46eX4you32Py+MrU6cIRXuUIzXS32VzIC3RlUuy1ZihKdW?= =?us-ascii?Q?qyxM0lL3Yz1JJ+GetAXYabVajh1IL9NNjGdbmVi1Sa0830ZAYLVWPV+OTBez?= =?us-ascii?Q?54svZmNn5hO6aKt10aLeYOfl8LOpgRzRAtMcz7vA+AGxOES6WShHfbmQmTbV?= =?us-ascii?Q?DVYcDyG5uPW+VFPYy2kf/KLHHuFTyx63DxNqXNfJPbUa56lr1AhyNx6C66Ml?= =?us-ascii?Q?KGTvEPKtutJTFvPwPkRkY29i44+xrsrunl4nde4AUjRfU8mF/qz75Gck8c9G?= =?us-ascii?Q?AQ2R1sET0NJs5axtebESdL6uW+2JS9AnuVsm+PYPeYtQ8JlqdBTggFAZ/VA6?= =?us-ascii?Q?cEdw17uXPfovNxY/KYiwdsaV68PnjExVxKnLtu82BxEQxnKt1p9IdwyDegG1?= =?us-ascii?Q?Jk9vRfwmmvLpHWeaEKfonfShKezr7+p6/WBxZdkF64Jy+IKWhhFSLYboNPCG?= =?us-ascii?Q?dkl3FNM5UvqfZag+f9ItthyhdjKrSvaqRvGiATp4bLSnHx3ZM3Nwb9Cajpo/?= =?us-ascii?Q?qDiCJGitFYERaQO/VHviI96ZP1rcoikCM0+9Fuu6dKbDtrU2ihKrgWEdHyVI?= =?us-ascii?Q?1yMM3jZgfNVACu0AxSG2FjEYV3a8DAoJ2woJ?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2025 18:47:47.8409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 958b6a6a-e0c3-4591-ce9e-08dd97ced0e6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022574.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB9044 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yevgeny Kliteynik Having adjacent accelerated modify header actions (so-called pattern-argument actions) may result in inconsistent outcome. These inconsistencies can take the form of writes to the same field or a read coupled with a write to the same field. The solution is to detect such dependencies and insert nops between the offending actions. The existing implementation had a few issues, which pretty much required a complete rewrite of the code that handles these dependencies. In the new implementation we're doing the following: * Checking any two adjacent actions for conflicts (not just odd-even pairs). * Marking 'set' and 'add' action fields as destination, rather than source, for the purposes of checking for conflicts. * Checking all types of actions ('add', 'set', 'copy') for dependencies. * Managing offsets of the args in the buffer - copy the action args to the right place in the buffer. * Checking that after inserting nops we're still within the number of supported actions - return an error otherwise. Signed-off-by: Vlad Dogaru Signed-off-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/action.c | 21 ++++-- .../mellanox/mlx5/core/steering/hws/pat_arg.c | 74 ++++++++++--------- .../mellanox/mlx5/core/steering/hws/pat_arg.h | 6 +- 3 files changed, 55 insertions(+), 46 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c = b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c index 64d115feef2c..fb62f3bc4bd4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c @@ -1190,14 +1190,15 @@ hws_action_create_modify_header_hws(struct mlx5hws_= action *action, struct mlx5hws_action_mh_pattern *pattern, u32 log_bulk_size) { + u16 num_actions, max_mh_actions =3D 0, hw_max_actions; struct mlx5hws_context *ctx =3D action->ctx; - u16 num_actions, max_mh_actions =3D 0; int i, ret, size_in_bytes; u32 pat_id, arg_id =3D 0; __be64 *new_pattern; size_t pat_max_sz; =20 pat_max_sz =3D MLX5HWS_ARG_CHUNK_SIZE_MAX * MLX5HWS_ARG_DATA_SIZE; + hw_max_actions =3D pat_max_sz / MLX5HWS_MODIFY_ACTION_SIZE; size_in_bytes =3D pat_max_sz * sizeof(__be64); new_pattern =3D kcalloc(num_of_patterns, size_in_bytes, GFP_KERNEL); if (!new_pattern) @@ -1211,10 +1212,14 @@ hws_action_create_modify_header_hws(struct mlx5hws_= action *action, =20 cur_num_actions =3D pattern[i].sz / MLX5HWS_MODIFY_ACTION_SIZE; =20 - mlx5hws_pat_calc_nop(pattern[i].data, cur_num_actions, - pat_max_sz / MLX5HWS_MODIFY_ACTION_SIZE, - &new_num_actions, &nop_locations, - &new_pattern[i * pat_max_sz]); + ret =3D mlx5hws_pat_calc_nop(pattern[i].data, cur_num_actions, + hw_max_actions, &new_num_actions, + &nop_locations, + &new_pattern[i * pat_max_sz]); + if (ret) { + mlx5hws_err(ctx, "Too many actions after nop insertion\n"); + goto free_new_pat; + } =20 action[i].modify_header.nop_locations =3D nop_locations; action[i].modify_header.num_of_actions =3D new_num_actions; @@ -2116,10 +2121,12 @@ static void hws_action_modify_write(struct mlx5hws_= send_engine *queue, if (unlikely(!new_arg_data)) return; =20 - for (i =3D 0, j =3D 0; i < num_of_actions; i++, j++) { - memcpy(&new_arg_data[j], arg_data, MLX5HWS_MODIFY_ACTION_SIZE); + for (i =3D 0, j =3D 0; j < num_of_actions; i++, j++) { if (BIT(i) & nop_locations) j++; + memcpy(&new_arg_data[j * MLX5HWS_MODIFY_ACTION_SIZE], + &arg_data[i * MLX5HWS_MODIFY_ACTION_SIZE], + MLX5HWS_MODIFY_ACTION_SIZE); } } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c index 78de19c074a7..51e4c551e0ef 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c @@ -490,8 +490,8 @@ hws_action_modify_get_target_fields(u8 action_type, __b= e64 *pattern, switch (action_type) { case MLX5_ACTION_TYPE_SET: case MLX5_ACTION_TYPE_ADD: - *src_field =3D MLX5_GET(set_action_in, pattern, field); - *dst_field =3D INVALID_FIELD; + *src_field =3D INVALID_FIELD; + *dst_field =3D MLX5_GET(set_action_in, pattern, field); break; case MLX5_ACTION_TYPE_COPY: *src_field =3D MLX5_GET(copy_action_in, pattern, src_field); @@ -522,57 +522,59 @@ bool mlx5hws_pat_verify_actions(struct mlx5hws_contex= t *ctx, __be64 pattern[], s return true; } =20 -void mlx5hws_pat_calc_nop(__be64 *pattern, size_t num_actions, - size_t max_actions, size_t *new_size, - u32 *nop_locations, __be64 *new_pat) +int mlx5hws_pat_calc_nop(__be64 *pattern, size_t num_actions, + size_t max_actions, size_t *new_size, + u32 *nop_locations, __be64 *new_pat) { - u16 prev_src_field =3D 0, prev_dst_field =3D 0; + u16 prev_src_field =3D INVALID_FIELD, prev_dst_field =3D INVALID_FIELD; u16 src_field, dst_field; u8 action_type; + bool dependent; size_t i, j; =20 *new_size =3D num_actions; *nop_locations =3D 0; =20 if (num_actions =3D=3D 1) - return; + return 0; =20 for (i =3D 0, j =3D 0; i < num_actions; i++, j++) { - action_type =3D MLX5_GET(set_action_in, &pattern[i], action_type); + if (j >=3D max_actions) + return -EINVAL; =20 + action_type =3D MLX5_GET(set_action_in, &pattern[i], action_type); hws_action_modify_get_target_fields(action_type, &pattern[i], &src_field, &dst_field); - if (i % 2) { - if (action_type =3D=3D MLX5_ACTION_TYPE_COPY && - (prev_src_field =3D=3D src_field || - prev_dst_field =3D=3D dst_field)) { - /* need Nop */ - *new_size +=3D 1; - *nop_locations |=3D BIT(i); - memset(&new_pat[j], 0, MLX5HWS_MODIFY_ACTION_SIZE); - MLX5_SET(set_action_in, &new_pat[j], - action_type, - MLX5_MODIFICATION_TYPE_NOP); - j++; - } else if (prev_src_field =3D=3D src_field) { - /* need Nop */ - *new_size +=3D 1; - *nop_locations |=3D BIT(i); - MLX5_SET(set_action_in, &new_pat[j], - action_type, - MLX5_MODIFICATION_TYPE_NOP); - j++; - } - } - memcpy(&new_pat[j], &pattern[i], MLX5HWS_MODIFY_ACTION_SIZE); - /* check if no more space */ - if (j > max_actions) { - *new_size =3D num_actions; - *nop_locations =3D 0; - return; + + /* For every action, look at it and the previous one. The two + * actions are dependent if: + */ + dependent =3D + (i > 0) && + /* At least one of the actions is a write and */ + (dst_field !=3D INVALID_FIELD || + prev_dst_field !=3D INVALID_FIELD) && + /* One reads from the other's source */ + (dst_field =3D=3D prev_src_field || + src_field =3D=3D prev_dst_field || + /* Or both write to the same destination */ + dst_field =3D=3D prev_dst_field); + + if (dependent) { + *new_size +=3D 1; + *nop_locations |=3D BIT(i); + memset(&new_pat[j], 0, MLX5HWS_MODIFY_ACTION_SIZE); + MLX5_SET(set_action_in, &new_pat[j], action_type, + MLX5_MODIFICATION_TYPE_NOP); + j++; + if (j >=3D max_actions) + return -EINVAL; } =20 + memcpy(&new_pat[j], &pattern[i], MLX5HWS_MODIFY_ACTION_SIZE); prev_src_field =3D src_field; prev_dst_field =3D dst_field; } + + return 0; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h index 91bd2572a341..7fbd8dc7aa18 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h @@ -96,7 +96,7 @@ int mlx5hws_arg_write_inline_arg_data(struct mlx5hws_cont= ext *ctx, u8 *arg_data, size_t data_size); =20 -void mlx5hws_pat_calc_nop(__be64 *pattern, size_t num_actions, - size_t max_actions, size_t *new_size, - u32 *nop_locations, __be64 *new_pat); +int mlx5hws_pat_calc_nop(__be64 *pattern, size_t num_actions, + size_t max_actions, size_t *new_size, + u32 *nop_locations, __be64 *new_pat); #endif /* MLX5HWS_PAT_ARG_H_ */ --=20 2.31.1