From nobody Fri Dec 19 20:34:37 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CF5D225787; Fri, 16 May 2025 19:47:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747424829; cv=none; b=jx0xi9ILhMuw+LZgZCwpcT+2WrGEGXsU4DQ5nudvVLhEmJu1jpV3JzkwBmtqrsTEoEUUTu6FjdUz7sTAn02J9Fcvh3scw7dbHTtNfo9dL6/S4nR8mLJiOXxHGQBelg/CBozBi8D40HSYCbYZJayca6txoKqjzfSTFbdee8ayryg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747424829; c=relaxed/simple; bh=NmcPA58Z0Wmk80BoU52BQrjV8K1ecKlvNGjSyfTX0sg=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=ffyCGGcTodqtM3dnMDsPhhyWBZbEJ/n/boYydfZorpxq/Q2KMlsiyDPsuZaltF/x8o26wA3c/FSxcxd0+HgwEOpY09U/YZ+o9ExqmAskAKsV8c4iFkxx8tHoBYzSa6pvZCacLQSimxlX6MYFnkaJrjpds/Ma9POaLCtmqr0MRhY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=s8QCsdcu; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2XRYW4Ao; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="s8QCsdcu"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2XRYW4Ao" Date: Fri, 16 May 2025 19:47:05 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1747424826; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FX7KenXNCGb4+rHp2sJNNx8oPtnzxKarimgf8B+xjII=; b=s8QCsdcu0LoIDuHaZWscv5bbvY84v1I5D75Td9wZ/+Y189Bt4uZbdxRyVAuD1OXRUheSQP H2s4CuFfpk+rhW84ltIwbi90G1s2mDskpgHasSWInhiqos2KrAbzETAew9E2d4s20DbvFY EPDkbrGTR9pEAU2kXIXndGGLEq3qdeddXJ9F5gFoMHLtdyXb4nO/UlC4fRdOBu1qcy7rf5 ZbK42zR/mZS4vGsW/A2vNTbnr7r5tqynRyv6Co3gCzTrA/IZsMvd3iwkUe9sfDucdJsy91 GnoK1hGufVoz0c4vTOFEJl+hBdVNIn0rTdeZRTZBuZn75ZV1YYnFpWZ9pqUdqQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1747424826; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FX7KenXNCGb4+rHp2sJNNx8oPtnzxKarimgf8B+xjII=; b=2XRYW4AoN9fbCYB4AkShoZpydUPVrpHou8/vb89+oCZwq1Bvvc6zSo/P4nL3dG/M4FgtuE 7nh6Q0GIt/Qlr6AA== From: "tip-bot2 for Marc Zyngier" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/msi] PCI: xgene: Convert to MSI parent infrastructure Cc: Marc Zyngier , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250513172819.2216709-9-maz@kernel.org> References: <20250513172819.2216709-9-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174742482522.406.3140173637801608960.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/msi branch of tip: Commit-ID: ae79351ef280805e0881fd2011b74ed008a4e151 Gitweb: https://git.kernel.org/tip/ae79351ef280805e0881fd2011b74ed00= 8a4e151 Author: Marc Zyngier AuthorDate: Tue, 13 May 2025 18:28:18 +01:00 Committer: Thomas Gleixner CommitterDate: Fri, 16 May 2025 21:32:20 +02:00 PCI: xgene: Convert to MSI parent infrastructure In an effort to move ARM64 away from the legacy MSI setup, convert the XGENE PCIe driver to the MSI-parent infrastructure and let each device have its own MSI domain. [ tglx: Moved the struct out of the function call argument ] Signed-off-by: Marc Zyngier Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20250513172819.2216709-9-maz@kernel.org --- drivers/pci/controller/Kconfig | 1 +- drivers/pci/controller/pci-xgene-msi.c | 53 +++++++++---------------- 2 files changed, 21 insertions(+), 33 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 98a62f4..205e0e3 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -304,6 +304,7 @@ config PCI_XGENE_MSI bool "X-Gene v1 PCIe MSI feature" depends on PCI_XGENE depends on PCI_MSI + select IRQ_MSI_LIB default y help Say Y here if you want PCIe MSI support for the APM X-Gene v1 SoC. diff --git a/drivers/pci/controller/pci-xgene-msi.c b/drivers/pci/controlle= r/pci-xgene-msi.c index 69a9c0a..b05ec8b 100644 --- a/drivers/pci/controller/pci-xgene-msi.c +++ b/drivers/pci/controller/pci-xgene-msi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -32,7 +33,6 @@ struct xgene_msi_group { struct xgene_msi { struct device_node *node; struct irq_domain *inner_domain; - struct irq_domain *msi_domain; u64 msi_addr; void __iomem *msi_regs; unsigned long *bitmap; @@ -44,20 +44,6 @@ struct xgene_msi { /* Global data */ static struct xgene_msi xgene_msi_ctrl; =20 -static struct irq_chip xgene_msi_top_irq_chip =3D { - .name =3D "X-Gene1 MSI", - .irq_enable =3D pci_msi_unmask_irq, - .irq_disable =3D pci_msi_mask_irq, - .irq_mask =3D pci_msi_mask_irq, - .irq_unmask =3D pci_msi_unmask_irq, -}; - -static struct msi_domain_info xgene_msi_domain_info =3D { - .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_PCI_MSIX), - .chip =3D &xgene_msi_top_irq_chip, -}; - /* * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where * n is group number (0..F), x is index of registers in each group (0..7) @@ -235,34 +221,35 @@ static void xgene_irq_domain_free(struct irq_domain *= domain, irq_domain_free_irqs_parent(domain, virq, nr_irqs); } =20 -static const struct irq_domain_ops msi_domain_ops =3D { +static const struct irq_domain_ops xgene_msi_domain_ops =3D { .alloc =3D xgene_irq_domain_alloc, .free =3D xgene_irq_domain_free, }; =20 +static const struct msi_parent_ops xgene_msi_parent_ops =3D { + .supported_flags =3D (MSI_GENERIC_FLAGS_MASK | + MSI_FLAG_PCI_MSIX), + .required_flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | + MSI_FLAG_USE_DEF_CHIP_OPS), + .bus_select_token =3D DOMAIN_BUS_PCI_MSI, + .init_dev_msi_info =3D msi_lib_init_dev_msi_info, +}; + static int xgene_allocate_domains(struct xgene_msi *msi) { - msi->inner_domain =3D irq_domain_add_linear(NULL, NR_MSI_VEC, - &msi_domain_ops, msi); - if (!msi->inner_domain) - return -ENOMEM; - - msi->msi_domain =3D pci_msi_create_irq_domain(of_fwnode_handle(msi->node), - &xgene_msi_domain_info, - msi->inner_domain); - - if (!msi->msi_domain) { - irq_domain_remove(msi->inner_domain); - return -ENOMEM; - } - - return 0; + struct irq_domain_info info =3D { + .fwnode =3D of_fwnode_handle(msi->node), + .ops =3D &xgene_msi_domain_ops, + .size =3D NR_MSI_VEC, + .host_data =3D msi, + }; + + msi->inner_domain =3D msi_create_parent_irq_domain(&info, &xgene_msi_pare= nt_ops); + return msi->inner_domain ? 0 : -ENOMEM; } =20 static void xgene_free_domains(struct xgene_msi *msi) { - if (msi->msi_domain) - irq_domain_remove(msi->msi_domain); if (msi->inner_domain) irq_domain_remove(msi->inner_domain); }