From nobody Fri Dec 19 20:36:29 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A19D20B7FE; Fri, 16 May 2025 09:01:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747386065; cv=none; b=AF9lqzsPVtgjsRVimjePTdX/EfLJ6CnWaZVECya6GkQmSEQe+8Er64AYN3Ja2BKVbvKGKWa3t7Hodj0mXvuhBV5LsjyeeS78OzyLqBtjp286zg5hvJHMHQWqjBlipkfCvs73CcQ9QcY9QwFoIUChl/GZU6OQXts4/mIZHXQuh3w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747386065; c=relaxed/simple; bh=f/yda2gE3MEL/hTumrVExVXdBE/L3M+sjzGXRQ1G5SY=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=Qu0cnFpFYe3MDezIaWzMzpMZinlen0209B0CzpQdZT4/DDGHINFfJcXFZRLIAY5DLgWan1b9MtQnbDT/Iaj3eJbrkWTmV8w5BZD/wosImvPKHrCLjV0jXuYs2/KZlBUtFg3UXLR0nRXgHNtfipd1ShBr8xweTSKNhVT1UZ55ZK8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ircdNigy; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ws7Yfku7; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ircdNigy"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ws7Yfku7" Date: Fri, 16 May 2025 09:01:00 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1747386061; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S18cehFSUHefq6PTrUYNOrDbKRuIsk1buU25at9T5Ww=; b=ircdNigyt5dHgbl2Tn9YTpUCjt6ql/24KZH5moeJikIwz3OJQsiMxIg970nXqiRueIgnCG Y7sNMVjwN2yebq3VS0161A6uYmLCWM8rsGa7yh4OTqRezGtB6f0KToox7ivi9uqzEKzkpH wiYjl7P77kpw7CsAmmju8aCrCIQ6HRsqGLl/4I74mS/75JvRIh3/1LreWwlTPVAcz8o4FI 44BpO2ZDDpgiFvrJ6UpjS4v/M9CSchg2+0GfeImVpv5f7rWXOpHvrcPIbQ2YMx7sbznrFo 9y2FkCbD8BNEl2aqqiRj+o3IXUPGfBoNq+lfHujB1V6rk83e9PkJie39S61sfw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1747386061; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S18cehFSUHefq6PTrUYNOrDbKRuIsk1buU25at9T5Ww=; b=ws7Yfku7V7LcxZFuGnj931PSGmHMZBoUhbG1QosqZ9dK1n0gOB2vYjThlxj8JKxg1ZIv8h Yz2B59T3U1wUuxCw== From: "tip-bot2 for Ahmed S. Darwish" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/core] x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2() Cc: "Ahmed S. Darwish" , Ingo Molnar , "H. Peter Anvin" , Andrew Cooper , John Ogness , x86-cpuid@lists.linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250508150240.172915-6-darwi@linutronix.de> References: <20250508150240.172915-6-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174738606068.406.9695253977424825815.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/core branch of tip: Commit-ID: e7df7289f1481993c9f326aea801323a1d3d0c5f Gitweb: https://git.kernel.org/tip/e7df7289f1481993c9f326aea801323a1= d3d0c5f Author: Ahmed S. Darwish AuthorDate: Thu, 08 May 2025 17:02:34 +02:00 Committer: Ingo Molnar CommitterDate: Fri, 16 May 2025 10:49:48 +02:00 x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2() Rename the CPUID(0x2) register accessor function: cpuid_get_leaf_0x2_regs(regs) to: cpuid_leaf_0x2(regs) for consistency with other accessors that return full CPUID registers outputs like: cpuid_leaf(regs) cpuid_subleaf(regs) In the same vein, rename the CPUID(0x2) iteration macro: for_each_leaf_0x2_entry() to: for_each_cpuid_0x2_desc() to include "cpuid" in the macro name, and since what is iterated upon is CPUID(0x2) cache and TLB "descriptos", not "entries". Prefix an underscore to that iterator macro parameters, so that the newly renamed 'desc' parameter do not get mixed with "union leaf_0x2_regs :: desc[]" in the macro's implementation. Adjust all the affected call-sites accordingly. While at it, use "CPUID(0x2)" instead of "CPUID leaf 0x2" as this is the recommended style. No change in functionality intended. Signed-off-by: Ahmed S. Darwish Signed-off-by: Ingo Molnar Cc: H. Peter Anvin Cc: Andrew Cooper Cc: John Ogness Cc: x86-cpuid@lists.linux.dev Link: https://lore.kernel.org/r/20250508150240.172915-6-darwi@linutronix.de --- arch/x86/include/asm/cpuid/api.h | 40 +++++++++++++++---------------- arch/x86/kernel/cpu/cacheinfo.c | 4 +-- arch/x86/kernel/cpu/intel.c | 4 +-- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index c0211fc..ccf20c6 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -216,17 +216,17 @@ static inline u32 hypervisor_cpuid_base(const char *s= ig, u32 leaves) */ =20 /** - * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output + * cpuid_leaf_0x2() - Return sanitized CPUID(0x2) register output * @regs: Output parameter * - * Query CPUID leaf 0x2 and store its output in @regs. Force set any + * Query CPUID(0x2) and store its output in @regs. Force set any * invalid 1-byte descriptor returned by the hardware to zero (the NULL * cache/TLB descriptor) before returning it to the caller. * - * Use for_each_leaf_0x2_entry() to iterate over the register output in + * Use for_each_cpuid_0x2_desc() to iterate over the register output in * parsed form. */ -static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs) +static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs) { cpuid_leaf(0x2, regs); =20 @@ -251,34 +251,34 @@ static inline void cpuid_get_leaf_0x2_regs(union leaf= _0x2_regs *regs) } =20 /** - * for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors - * @regs: Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs() - * @__ptr: u8 pointer, for macro internal use only - * @entry: Pointer to parsed descriptor information at each iteration + * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors + * @_regs: CPUID(0x2) register output, as returned by cpuid_leaf_0x2() + * @_ptr: u8 pointer, for macro internal use only + * @_desc: Pointer to the parsed CPUID(0x2) descriptor at each iteration * - * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers - * @regs. Provide the parsed information for each descriptor through @ent= ry. + * Loop over the 1-byte descriptors in the passed CPUID(0x2) output regist= ers + * @_regs. Provide the parsed information for each descriptor through @_d= esc. * - * To handle cache-specific descriptors, switch on @entry->c_type. For TLB - * descriptors, switch on @entry->t_type. + * To handle cache-specific descriptors, switch on @_desc->c_type. For TLB + * descriptors, switch on @_desc->t_type. * * Example usage for cache descriptors:: * - * const struct leaf_0x2_table *entry; + * const struct leaf_0x2_table *desc; * union leaf_0x2_regs regs; * u8 *ptr; * - * cpuid_get_leaf_0x2_regs(®s); - * for_each_leaf_0x2_entry(regs, ptr, entry) { - * switch (entry->c_type) { + * cpuid_leaf_0x2(®s); + * for_each_cpuid_0x2_desc(regs, ptr, desc) { + * switch (desc->c_type) { * ... * } * } */ -#define for_each_leaf_0x2_entry(regs, __ptr, entry) \ - for (__ptr =3D &(regs).desc[1]; \ - __ptr < &(regs).desc[16] && (entry =3D &cpuid_0x2_table[*__ptr]); \ - __ptr++) +#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc) \ + for (_ptr =3D &(_regs).desc[1]; \ + _ptr < &(_regs).desc[16] && (_desc =3D &cpuid_0x2_table[*_ptr]); \ + _ptr++) =20 /* * CPUID(0x80000006) parsing: diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 6d61f7d..b6349c1 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -388,8 +388,8 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) if (c->cpuid_level < 2) return; =20 - cpuid_get_leaf_0x2_regs(®s); - for_each_leaf_0x2_entry(regs, ptr, entry) { + cpuid_leaf_0x2(®s); + for_each_cpuid_0x2_desc(regs, ptr, entry) { switch (entry->c_type) { case CACHE_L1_INST: l1i +=3D entry->c_size; break; case CACHE_L1_DATA: l1d +=3D entry->c_size; break; diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 7f8ca29..f8141b5 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -716,8 +716,8 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c) if (c->cpuid_level < 2) return; =20 - cpuid_get_leaf_0x2_regs(®s); - for_each_leaf_0x2_entry(regs, ptr, entry) + cpuid_leaf_0x2(®s); + for_each_cpuid_0x2_desc(regs, ptr, entry) intel_tlb_lookup(entry); }