From nobody Sun Feb 8 10:33:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2B342571DD; Thu, 15 May 2025 17:17:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747329439; cv=none; b=KnZ5f9ZVBR2jIMrCMD+dsui9OJF3NENG1791l2PTzoTSfFnlbtiaaVheUr4bLMVooMEHMBa35IMZL/dx0cVq9tpvmlfRsDV82wmKnlMSGPrPk/Bm5BhNJjUGFbw74L5ULXoJ7sf4h+4nAKB2f9DLPXbyG9spYBAvLjXgBt038Pk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747329439; c=relaxed/simple; bh=/CmgR/BeKbegcWFBuOXteK1BblZKwjsFXZTh8XvE3PI=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=XJ2MWsixJHa4Omty9qkkA+y/X7m0V9SL7WVgGplXN3nFPTgEYBtF0Nt9Iv/vA65Km6owhLpqPrzzQd3QNdNhJHlHyQ2hxzIy5x3m87jmzJf9zMy+01UBnAe7OAyrDdYfwJa3ZDXM+Yq4SWcpj74Kre5wbwqGsX+pZKY0tMDVXfY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=dminbUzs; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=OkDAVFQJ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="dminbUzs"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="OkDAVFQJ" Date: Thu, 15 May 2025 17:17:15 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1747329436; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iblZEk3+jIzM7xzAWy9XgL8yS0cnrQ7pMPyHYsOTPXM=; b=dminbUzslAXZtSJvADTJhM4AMm2qlC2V2j72Sl/LdO8cHV9yfuLbfhX6XgW7NLr76O59ua Gsjqy1u+s/eMbBUyia2g8E5vXmc/XIGkIbG0u7LsQ5P4Nx+eWaOQoR8C0Vdl9KizJ5jCwF R6b+fFjbGgcZmJEAhSYwsngWJY1HwVcN7QvCWjbuW7zTLTjWWUMIdYcqGEX9buhTukElA8 4tNLC6RQfYGjBAvPeF47hcS3gdSdbSJExWpB369L+DOyhujXsyQ/qDVLbizkm7M5FpbdAf i8VcCuqkNG534F9BrM+7sdA7V3agsF4iP9xbPxykGAMmu8zqnaFoQk6/f6b31Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1747329436; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iblZEk3+jIzM7xzAWy9XgL8yS0cnrQ7pMPyHYsOTPXM=; b=OkDAVFQJj/U68dYnQtbzGxzkz8J94RT6umYcveWqfBBbNm2EQxy1CABp+uy+TEZ9GSwf0W oAIwz6vApr/xb+Dw== From: "tip-bot2 for Ahmed S. Darwish" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/core] x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter Cc: "Ahmed S. Darwish" , Ingo Molnar , "H. Peter Anvin" , Andrew Cooper , John Ogness , x86-cpuid@lists.linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250508150240.172915-7-darwi@linutronix.de> References: <20250508150240.172915-7-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174732943520.406.17897590489687675996.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/core branch of tip: Commit-ID: 7f6b49644c6cadd9682075bc2dd6a1ba2afd55d8 Gitweb: https://git.kernel.org/tip/7f6b49644c6cadd9682075bc2dd6a1ba2= afd55d8 Author: Ahmed S. Darwish AuthorDate: Thu, 08 May 2025 17:02:35 +02:00 Committer: Ingo Molnar CommitterDate: Thu, 15 May 2025 18:48:10 +02:00 x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter The CPUID(0x2) descriptors iterator has been renamed from: for_each_leaf_0x2_entry() to: for_each_cpuid_0x2_desc() since it iterates over CPUID(0x2) cache and TLB "descriptors", not "entries". In the macro's x86/cacheinfo call-site, rename the parameter denoting the parsed descriptor at each iteration from 'entry' to 'desc'. Signed-off-by: Ahmed S. Darwish Signed-off-by: Ingo Molnar Cc: H. Peter Anvin Cc: Andrew Cooper Cc: John Ogness Cc: x86-cpuid@lists.linux.dev Link: https://lore.kernel.org/r/20250508150240.172915-7-darwi@linutronix.de --- arch/x86/kernel/cpu/cacheinfo.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index b6349c1..adfa7e8 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -381,7 +381,7 @@ static void intel_cacheinfo_done(struct cpuinfo_x86 *c,= unsigned int l3, static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) { unsigned int l1i =3D 0, l1d =3D 0, l2 =3D 0, l3 =3D 0; - const struct leaf_0x2_table *entry; + const struct leaf_0x2_table *desc; union leaf_0x2_regs regs; u8 *ptr; =20 @@ -389,12 +389,12 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) return; =20 cpuid_leaf_0x2(®s); - for_each_cpuid_0x2_desc(regs, ptr, entry) { - switch (entry->c_type) { - case CACHE_L1_INST: l1i +=3D entry->c_size; break; - case CACHE_L1_DATA: l1d +=3D entry->c_size; break; - case CACHE_L2: l2 +=3D entry->c_size; break; - case CACHE_L3: l3 +=3D entry->c_size; break; + for_each_cpuid_0x2_desc(regs, ptr, desc) { + switch (desc->c_type) { + case CACHE_L1_INST: l1i +=3D desc->c_size; break; + case CACHE_L1_DATA: l1d +=3D desc->c_size; break; + case CACHE_L2: l2 +=3D desc->c_size; break; + case CACHE_L3: l3 +=3D desc->c_size; break; } }