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Sun, 11 May 2025 12:39:27 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch , Vlad Dogaru , Yevgeny Kliteynik , Gal Pressman Subject: [PATCH net-next 07/10] net/mlx5: HWS, fix counting of rules in the matcher Date: Sun, 11 May 2025 22:38:07 +0300 Message-ID: <1746992290-568936-8-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1746992290-568936-1-git-send-email-tariqt@nvidia.com> References: <1746992290-568936-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E5F:EE_|PH7PR12MB5655:EE_ X-MS-Office365-Filtering-Correlation-Id: 1406fbfd-007c-4cbe-020d-08dd90c3914a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?qVuPo8hwnnFeZVMjaJdQ/+AW9C8dzRB2XrQHBmFFEOWf+L9QNwJA7y3VlX7u?= =?us-ascii?Q?G8NcIB3lqOgNg9v5A6gC054jmHi4nKeiVI4jBvMhd2cQ2Vh5eslcmAtgItSy?= =?us-ascii?Q?ot8FH9oNc7nvsJB/8exr4iwQhvjdkDrguys4sd8zoRNVuVvtFgfX2qBU1z2Y?= =?us-ascii?Q?O0lmfbqVVfV319mJx37rBD718CbyT6pESmBQVxtKU3eqoZqOr05tF1h03YIu?= =?us-ascii?Q?vreTnbnZHB4iinT/fphwRgSCJst5FsB9+iilPQCmfUpFotLqYheugmjJGdHJ?= =?us-ascii?Q?VYGvqR2JAG+/z18eS6ZNg18mTNtlZ5NRrqC8ULY2R01wRfdOcfFAXkO6uwmE?= =?us-ascii?Q?9+noowCMClmOb4QwqdwZyznvtch50L7VXSUhJ2YjhWiceSRbjhVQNBiGh2A/?= =?us-ascii?Q?hsfusM44iMe2sF66QofW00SCP/wTaJ6h4XU1tJbOZnGTlweiQWqZIYjkI6vV?= =?us-ascii?Q?tfRVba5VLubd6f7os7bTCSoU9FtOFxwyo3aNYNO2RXfWIzC2AXmeIfd+p/+4?= =?us-ascii?Q?YE9MASISikg3iZ49BxycjEtWcE9STHoMjuRo7Yau3o4adFdlLUaY5qF0D/n2?= =?us-ascii?Q?bsJmxybVyqfHPv7Zc5gPJG64t+WGl/BeNP3t+3CSb7J305RZK3h+10q18FeJ?= =?us-ascii?Q?E4K2D0rtCgb4zgNoZqA4IoPgsaiw/cLdlzsX1+Ud0dPDICJgz8okHAQloMDs?= =?us-ascii?Q?HikTKykLR9PGJhG1oirVID34H89hzrUv3gU8zJ1ub3nyoyu/RbIRfhZE0DwV?= =?us-ascii?Q?TvhQ+X7It6Ov4kTb9d4cmlw53N72hxlH3XVBsNHVwHU6kOhse3tTuGkuM5oq?= =?us-ascii?Q?UJWFS3XQmZq98b34/MkJEjpEPxkL7/Oblo1W+tweo0TLuQWRjDM7QtAYG1Nu?= =?us-ascii?Q?d7Ox8S0va/1y6f918wrk4d6/JusAkmdqVGr1+ibnkgRUVw/SOg4pKM5NGw5n?= =?us-ascii?Q?Gg/JetAj6DdsXyLzZk8F0Fb1yYdrtDe3s2fBElYl7UvXz/4s2WW3Tvf0jh2Y?= =?us-ascii?Q?89b36Kww07EsSpJP9ffppUL3dR5HvCKZ0hdaXS1bUZow3CQhXWZucD2gEjoV?= =?us-ascii?Q?B7cWZ+xomtDOqM85xIUJXaJJbub/fzXErIc14TeL0vEzjoDvtACmMYZ3QWUX?= =?us-ascii?Q?oLe1+kJoZhtOAOwgoASs8hbxjj60RCQkg1NDT0Hq/c96ObKFT6xryG0ZGQlL?= =?us-ascii?Q?VTpKueuaKGUJg8CEtjuhkUxeXCr866G+yCs1LU3qBvaRyJS8qsn6zEUjnwIt?= =?us-ascii?Q?bqR+7cNHEzH0beYjbDjKB2iH0E9nxht2fzp++gQCvkOHp3QgAAqPnIQV+sfF?= =?us-ascii?Q?BsVcRTKJi4lhDgG8s/KztlvTPs3rc7GotjdschKzvVBoMbvl/efqxOlHxg1P?= =?us-ascii?Q?T4Ndr4DD8+tbXpD8QgS/PjkhfaeiLltIFvj/n2LWOLNvuG9E+CvRkULoPAJz?= =?us-ascii?Q?AGOgJIjLardl5vQRwas8K8mfW8otp7Z9pcWOeFxr9hGSu9utt03ggMxq+rK/?= =?us-ascii?Q?ZKI1KOL4xomljMN8ZJn98QqQoDz2UI2Ztr1Z?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2025 19:39:38.5104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1406fbfd-007c-4cbe-020d-08dd90c3914a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E5F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5655 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yevgeny Kliteynik Currently the counter that counts number of rules in a matcher is increased only when rule insertion is completed. In a multi-threaded usecase this can lead to a scenario that many rules can be in process of insertion in the same matcher, while none of them has completed the insertion and the rule counter is not updated. This results in a rule insertion failure for many of them at first attempt, which leads to all of them requiring rehash and requiring locking of all the queue locks. This patch fixes the case by increasing the rule counter in the beginning of insertion process and decreasing in case of any failure. Signed-off-by: Vlad Dogaru Signed-off-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c b/d= rivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c index dce2605fc99b..7d991a61eeb3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c @@ -341,16 +341,12 @@ static void hws_bwc_rule_list_add(struct mlx5hws_bwc_= rule *bwc_rule, u16 idx) { struct mlx5hws_bwc_matcher *bwc_matcher =3D bwc_rule->bwc_matcher; =20 - atomic_inc(&bwc_matcher->num_of_rules); bwc_rule->bwc_queue_idx =3D idx; list_add(&bwc_rule->list_node, &bwc_matcher->rules[idx]); } =20 static void hws_bwc_rule_list_remove(struct mlx5hws_bwc_rule *bwc_rule) { - struct mlx5hws_bwc_matcher *bwc_matcher =3D bwc_rule->bwc_matcher; - - atomic_dec(&bwc_matcher->num_of_rules); list_del_init(&bwc_rule->list_node); } =20 @@ -404,6 +400,7 @@ int mlx5hws_bwc_rule_destroy_simple(struct mlx5hws_bwc_= rule *bwc_rule) mutex_lock(queue_lock); =20 ret =3D hws_bwc_rule_destroy_hws_sync(bwc_rule, &attr); + atomic_dec(&bwc_matcher->num_of_rules); hws_bwc_rule_list_remove(bwc_rule); =20 mutex_unlock(queue_lock); @@ -840,7 +837,7 @@ int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_r= ule *bwc_rule, } =20 /* check if number of rules require rehash */ - num_of_rules =3D atomic_read(&bwc_matcher->num_of_rules); + num_of_rules =3D atomic_inc_return(&bwc_matcher->num_of_rules); =20 if (unlikely(hws_bwc_matcher_rehash_size_needed(bwc_matcher, num_of_rules= ))) { mutex_unlock(queue_lock); @@ -854,6 +851,7 @@ int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_r= ule *bwc_rule, bwc_matcher->size_log - MLX5HWS_BWC_MATCHER_SIZE_LOG_STEP, bwc_matcher->size_log, ret); + atomic_dec(&bwc_matcher->num_of_rules); return ret; } =20 @@ -887,6 +885,7 @@ int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_r= ule *bwc_rule, =20 if (ret) { mlx5hws_err(ctx, "BWC rule insertion: rehash failed (%d)\n", ret); + atomic_dec(&bwc_matcher->num_of_rules); return ret; } =20 @@ -902,6 +901,7 @@ int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_r= ule *bwc_rule, if (unlikely(ret)) { mutex_unlock(queue_lock); mlx5hws_err(ctx, "BWC rule insertion failed (%d)\n", ret); + atomic_dec(&bwc_matcher->num_of_rules); return ret; } =20 --=20 2.31.1