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Thu, 8 May 2025 22:49:22 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Jiri Pirko , Gal Pressman , "Leon Romanovsky" , Donald Hunter , "Jiri Pirko" , Jonathan Corbet , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , , , , , Moshe Shemesh , Mark Bloch , Carolina Jubran , Cosmin Ratiu Subject: [PATCH net-next V9 2/5] net/mlx5: Add no-op implementation for setting tc-bw on rate objects Date: Fri, 9 May 2025 08:43:06 +0300 Message-ID: <1746769389-463484-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1746769389-463484-1-git-send-email-tariqt@nvidia.com> References: <1746769389-463484-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003446:EE_|CH3PR12MB8511:EE_ X-MS-Office365-Filtering-Correlation-Id: f1badc82-3c18-4906-0ab1-08dd8ebd4981 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?2iZ9RBcVkYLAOK2PSnv8G3HZEn6IP1lnWsUMC6xzIktcuJzhFNBJ6l0igH0Q?= =?us-ascii?Q?yKvXQu+BvlClKsIQ1kmZ8L1L2Cd6PHu9cka3btlbBEhzIlFuI5TXiFATRlky?= =?us-ascii?Q?WNk7J8ch7g4RF4hiC30mqxmdDJiQVHKKID7PQye39i+KSIv50wbWQjhOUG+B?= =?us-ascii?Q?pEBr1su0ZvsXhRgXAGdLs1xwvZ2Pz3upzgga63TzvXRaxGnYNdnpSxNXY+eo?= =?us-ascii?Q?LHUPhkAJO4t5K0nxVNKXjt0Nd/jOf8wNfy2/A/KDsK5/vPQMKhHc9mQzuP2m?= =?us-ascii?Q?S9AA49vEKC0XlbwDNWMX9Rf4NvXUCh+/t8Xtyx4pCAjEgH/uFOkpxmieAj2a?= =?us-ascii?Q?3/J8/WIAzC7zHIDnHbCtfvppPynfHyWWxvmTMnWKrpFAUkEWlyTfv8TrGT2V?= =?us-ascii?Q?CAgOS1/p54hsJST2mnCA2qvJtDM9dplKD8GsMhWzIKqAorhS4ipBnvLrR9LJ?= =?us-ascii?Q?Ayfb+npRYpMn5HrQvqHkq5fjR0VivFOx7QEwQlG/UGLKS/JfHan4O+Eu6TT6?= =?us-ascii?Q?d62JYcYO9hxCNyskg120qhd+DLypqZqMwDzoQ7VOiUzJD198nROHdk4G96rl?= =?us-ascii?Q?i3hKgVq7bBbHxGqM4df3yRfwwdTCtwe2kGKB4MTRiFhSiQ2+/K/DJFQFMo1S?= =?us-ascii?Q?zaphUTnLt/dOZD0pC8lIvmTYboEPPG3poYkv/Q78RKULP8BuX6K/X1/OAchK?= =?us-ascii?Q?VgZQZmrYYPtqg/WRearLJ0lGgf07wsVP2/i5XA2yGtjT+ETU2gg5NDcqMlP/?= =?us-ascii?Q?o/lPdqs1rqMIBL1Sq/U3UMMSOsrxgGE+/grPQupcSOcUm5MdbkOmtl6t5r0g?= =?us-ascii?Q?nMOV3oLGQxCp8JXdg7GkIV+YMmQR75eJWV51tv0uo0wuoa6SHHAxY5XyxEt6?= =?us-ascii?Q?DEyjAsShAc925KjH6Jv/PdVkm0Nnc+2hbenuqHxHpbBqG6wVyQ2YdXC593/c?= =?us-ascii?Q?JqV2SRNd26l6pMC6e8lJR5Re6bOvoOwTbML/klCcLAINEJYIKwj6/k1tSr54?= =?us-ascii?Q?pwiZ4/PSF1/DQIqO9U1e1PBA49xLJ5WaZZb1KIdScWZeZ1A7j6vQvqU4vWzg?= =?us-ascii?Q?JPDhgV5RsG1dVs2gW+nJxmNP7/cftKk/up1mZog0yS8EnvgwjYKe7LtbuCvU?= =?us-ascii?Q?THVJJjtznsQ0I6tT5aIR55R8q96Vz4kKlpSTkAkK4h6AZc1Ojbie2d6+mLse?= =?us-ascii?Q?ruKPD1c6l6m1kN0yLZ5RGmhWgksnes3a/8K3jS90/x0nQSM2p6wQ885+XbKp?= =?us-ascii?Q?I6haklFxRUhSJYv/U/uqSDvlWAL6KavET8uTnUFKZwgHzdMsryoe7LCLaBmH?= =?us-ascii?Q?1fp7mAYKp5tIm78LG+a+U+LVNe48tvFYzUcQD7SAeMSMqXVwdRkKsOVYXSFD?= =?us-ascii?Q?zYtcCtA1uXLLfyCqdcZmZqYe7FwF3YoVFQocLA51hBmR6ylVjufEhMHgZzAM?= =?us-ascii?Q?agyv+8obCI417x/P38OBs1h7rqjmwvrNxMSKbLrU/bdfb4A+bYXWV6h4j9Bg?= =?us-ascii?Q?zk/j5PwgJRXGwJ9daO4hSFHo6sjJT71XnqjB?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2025 05:49:38.8623 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1badc82-3c18-4906-0ab1-08dd8ebd4981 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003446.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8511 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Introduce `mlx5_esw_devlink_rate_node_tc_bw_set()` and `mlx5_esw_devlink_rate_leaf_tc_bw_set()` with no-op logic. Future patches will add support for setting traffic class bandwidth on rate objects. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/devlink.c | 2 ++ .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 20 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/esw/qos.h | 8 ++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/devlink.c index 73cd74644378..47d3acd011cf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c @@ -323,6 +323,8 @@ static const struct devlink_ops mlx5_devlink_ops =3D { .eswitch_encap_mode_get =3D mlx5_devlink_eswitch_encap_mode_get, .rate_leaf_tx_share_set =3D mlx5_esw_devlink_rate_leaf_tx_share_set, .rate_leaf_tx_max_set =3D mlx5_esw_devlink_rate_leaf_tx_max_set, + .rate_leaf_tc_bw_set =3D mlx5_esw_devlink_rate_leaf_tc_bw_set, + .rate_node_tc_bw_set =3D mlx5_esw_devlink_rate_node_tc_bw_set, .rate_node_tx_share_set =3D mlx5_esw_devlink_rate_node_tx_share_set, .rate_node_tx_max_set =3D mlx5_esw_devlink_rate_node_tx_max_set, .rate_node_new =3D mlx5_esw_devlink_rate_node_new, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index b6ae384396b3..ec706e9352e1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -906,6 +906,26 @@ int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devli= nk_rate *rate_leaf, void * return err; } =20 +int mlx5_esw_devlink_rate_leaf_tc_bw_set(struct devlink_rate *rate_leaf, + void *priv, + u32 *tc_bw, + struct netlink_ext_ack *extack) +{ + NL_SET_ERR_MSG_MOD(extack, + "TC bandwidth shares are not supported on leafs"); + return -EOPNOTSUPP; +} + +int mlx5_esw_devlink_rate_node_tc_bw_set(struct devlink_rate *rate_node, + void *priv, + u32 *tc_bw, + struct netlink_ext_ack *extack) +{ + NL_SET_ERR_MSG_MOD(extack, + "TC bandwidth shares are not supported on nodes"); + return -EOPNOTSUPP; +} + int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node= , void *priv, u64 tx_share, struct netlink_ext_ack *extack) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.h index ed40ec8f027e..0a50982b0e27 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h @@ -21,6 +21,14 @@ int mlx5_esw_devlink_rate_leaf_tx_share_set(struct devli= nk_rate *rate_leaf, void u64 tx_share, struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devlink_rate *rate_leaf, = void *priv, u64 tx_max, struct netlink_ext_ack *extack); +int mlx5_esw_devlink_rate_leaf_tc_bw_set(struct devlink_rate *rate_node, + void *priv, + u32 *tc_bw, + struct netlink_ext_ack *extack); +int mlx5_esw_devlink_rate_node_tc_bw_set(struct devlink_rate *rate_node, + void *priv, + u32 *tc_bw, + struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node= , void *priv, u64 tx_share, struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_node_tx_max_set(struct devlink_rate *rate_node, = void *priv, --=20 2.31.1