From nobody Sun Feb 8 17:14:30 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C24D6238C1D; Fri, 2 May 2025 09:04:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176669; cv=none; b=Fc61sgfIj8ErBuRmAH5pAX5XUrm4ZFD/3g2buWGjYufUn4wyFlnsLCbXi+eIjW30S7spQbDLGF/+NRQ8NVaBn+IIrV/TtSZTxWXy4YN7/LSaQ6fS+JvN6kzNQvcTF5WJOyPVmXiEb6Qj2uWSCK1lmduWBS++W2zN+Rk5wkXlx2w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176669; c=relaxed/simple; bh=75PoCdKPZFa1RoiHHhbRMHtWeAVwKVPTWp6U8lcvRNo=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=Ccxpf3AfYDNT3XdWyJZEWTs3UFs7P9Nrud818BLev6vaM/RD49SlplKN8prlkoq1lYLh7n9oPXbjulap/niaBOoUsFxfNzq9YNEWSU3Hp//9Zqu72jtCqAPJPxXsCQNpGaVJi9oaG8GcxjCLM4XQl+umIS3wll6GJullREsNHx4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=jRhS8Vna; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=zqbp6jgP; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jRhS8Vna"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="zqbp6jgP" Date: Fri, 02 May 2025 09:04:25 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1746176666; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RMxjF1bX4Ze8WuRyZ2zByFplrog3UPADCpnqWGmjRZw=; b=jRhS8Vna/mkc70E+z0pKUGq6dCwjcdqOziGHUvPv9VGj4XdPIMstV4O8MSR5QT+5HavZau xRWwNaeklEIAz2oOOliXRpETahqVDD6WKU3zsuJUCe/NxgEXS0ySvuDuI9JgXbbLooVaua ZND8bLVzU+zekvyiSEy4v1eolclAgv9Io+ltsE6TpHTkWdhJxEHKhJ/59v3WVNZOdPBrxQ SlUBeGTrir2lBBbBHW05u2b1R6wJjjD+mj9YkheY+66i1FVNIo0HsorOgKsbl71ZKVWoAU +SKqO4InfPtBkubrjRzBkYk38U+aV07p7IAaulINhgS+Y9dxdDh1zvmqK3t2Qw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1746176666; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RMxjF1bX4Ze8WuRyZ2zByFplrog3UPADCpnqWGmjRZw=; b=zqbp6jgPgfkehVfSfJ/aJUg/1M+Dhx3vhWHqYFdb/AHIOR7Embf8P8iEfMtwjAMnCmqoqp tevymP4RuzOEtCCA== From: "tip-bot2 for Xin Li (Intel)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/merge] x86/msr: Convert the rdpmc() macro to an __always_inline function Cc: "Xin Li (Intel)" , Ingo Molnar , Dave Hansen , "Peter Zijlstra (Intel)" , Andy Lutomirski , Brian Gerst , Juergen Gross , "H. Peter Anvin" , Linus Torvalds , Kees Cook , Josh Poimboeuf , Uros Bizjak , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250427092027.1598740-6-xin@zytor.com> References: <20250427092027.1598740-6-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174617666516.22196.16604851134023882604.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/merge branch of tip: Commit-ID: 795ada52875fe61469f635f226d19a4cd733d1e8 Gitweb: https://git.kernel.org/tip/795ada52875fe61469f635f226d19a4cd= 733d1e8 Author: Xin Li (Intel) AuthorDate: Sun, 27 Apr 2025 02:20:17 -07:00 Committer: Ingo Molnar CommitterDate: Fri, 02 May 2025 10:26:56 +02:00 x86/msr: Convert the rdpmc() macro to an __always_inline function Functions offer type safety and better readability compared to macros. Additionally, always inline functions can match the performance of macros. Converting the rdpmc() macro into an always inline function is simple and straightforward, so just make the change. Moreover, the read result is now the returned value, further enhancing readability. Signed-off-by: Xin Li (Intel) Signed-off-by: Ingo Molnar Acked-by: Dave Hansen Acked-by: Peter Zijlstra (Intel) Cc: Andy Lutomirski Cc: Brian Gerst Cc: Juergen Gross Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Kees Cook Cc: Josh Poimboeuf Cc: Uros Bizjak Link: https://lore.kernel.org/r/20250427092027.1598740-6-xin@zytor.com --- arch/x86/events/amd/uncore.c | 2 +- arch/x86/events/core.c | 2 +- arch/x86/events/intel/core.c | 4 ++-- arch/x86/events/intel/ds.c | 2 +- arch/x86/include/asm/msr.h | 5 ++++- arch/x86/include/asm/paravirt.h | 4 +--- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 12 ++++++------ 7 files changed, 16 insertions(+), 15 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 42c833c..13c4cea 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -108,7 +108,7 @@ static void amd_uncore_read(struct perf_event *event) if (hwc->event_base_rdpmc < 0) rdmsrq(hwc->event_base, new); else - rdpmc(hwc->event_base_rdpmc, new); + new =3D rdpmc(hwc->event_base_rdpmc); =20 local64_set(&hwc->prev_count, new); delta =3D (new << COUNTER_SHIFT) - (prev << COUNTER_SHIFT); diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 600c0b6..bc92eba 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -135,7 +135,7 @@ u64 x86_perf_event_update(struct perf_event *event) */ prev_raw_count =3D local64_read(&hwc->prev_count); do { - rdpmc(hwc->event_base_rdpmc, new_raw_count); + new_raw_count =3D rdpmc(hwc->event_base_rdpmc); } while (!local64_try_cmpxchg(&hwc->prev_count, &prev_raw_count, new_raw_count)); =20 diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index e8eec16..33f3fd2 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2725,12 +2725,12 @@ static u64 intel_update_topdown_event(struct perf_e= vent *event, int metric_end,=20 =20 if (!val) { /* read Fixed counter 3 */ - rdpmc((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); + slots =3D rdpmc(3 | INTEL_PMC_FIXED_RDPMC_BASE); if (!slots) return 0; =20 /* read PERF_METRICS */ - rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); + metrics =3D rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS); } else { slots =3D val[0]; metrics =3D val[1]; diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 346db2f..4f52719 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2277,7 +2277,7 @@ intel_pmu_save_and_restart_reload(struct perf_event *= event, int count) WARN_ON(this_cpu_read(cpu_hw_events.enabled)); =20 prev_raw_count =3D local64_read(&hwc->prev_count); - rdpmc(hwc->event_base_rdpmc, new_raw_count); + new_raw_count =3D rdpmc(hwc->event_base_rdpmc); local64_set(&hwc->prev_count, new_raw_count); =20 /* diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 435a07b..fbeb313 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -217,7 +217,10 @@ static inline int rdmsrq_safe(u32 msr, u64 *p) return err; } =20 -#define rdpmc(counter, val) ((val) =3D native_read_pmc(counter)) +static __always_inline u64 rdpmc(int counter) +{ + return native_read_pmc(counter); +} =20 #endif /* !CONFIG_PARAVIRT_XXL */ =20 diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravir= t.h index faa0713..f272c4b 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -239,13 +239,11 @@ static inline int rdmsrq_safe(unsigned msr, u64 *p) return err; } =20 -static inline u64 paravirt_read_pmc(int counter) +static __always_inline u64 rdpmc(int counter) { return PVOP_CALL1(u64, cpu.read_pmc, counter); } =20 -#define rdpmc(counter, val) ((val) =3D paravirt_read_pmc(counter)) - static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned en= tries) { PVOP_VCALL2(cpu.alloc_ldt, ldt, entries); diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cp= u/resctrl/pseudo_lock.c index 15ff62d..61d7625 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -1019,8 +1019,8 @@ static int measure_residency_fn(struct perf_event_att= r *miss_attr, * used in L1 cache, second to capture accurate value that does not * include cache misses incurred because of instruction loads. */ - rdpmc(hit_pmcnum, hits_before); - rdpmc(miss_pmcnum, miss_before); + hits_before =3D rdpmc(hit_pmcnum); + miss_before =3D rdpmc(miss_pmcnum); /* * From SDM: Performing back-to-back fast reads are not guaranteed * to be monotonic. @@ -1028,8 +1028,8 @@ static int measure_residency_fn(struct perf_event_att= r *miss_attr, * before proceeding. */ rmb(); - rdpmc(hit_pmcnum, hits_before); - rdpmc(miss_pmcnum, miss_before); + hits_before =3D rdpmc(hit_pmcnum); + miss_before =3D rdpmc(miss_pmcnum); /* * Use LFENCE to ensure all previous instructions are retired * before proceeding. @@ -1051,8 +1051,8 @@ static int measure_residency_fn(struct perf_event_att= r *miss_attr, * before proceeding. */ rmb(); - rdpmc(hit_pmcnum, hits_after); - rdpmc(miss_pmcnum, miss_after); + hits_after =3D rdpmc(hit_pmcnum); + miss_after =3D rdpmc(miss_pmcnum); /* * Use LFENCE to ensure all previous instructions are retired * before proceeding.