From nobody Sat Feb 7 08:53:31 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0549023184A; Fri, 2 May 2025 09:04:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176669; cv=none; b=F9SHkgtcK0hpsgQKMpSSLx8oU82uOycTRUvEldBblJOxrWjGdX7FKW6Ug50yulUrufpvzgNSLMHu8hjUzImdqSYGha/OKBWHwLXqrUi0IPynn9eJ8wuzcgKvM+TToYJMudxuFotc12XvKbcZLlgzyRrmpJJvIUGEwQaFgFTJ9MQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176669; c=relaxed/simple; bh=iWoalFfOiR5cBfIxbmkxeh+P6hePxpp3M+EoTIhKWl8=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=fUUeSMI1kGmPV9le7K9HnYnv/H0AoBo+JPw+k13m0C3Ya3lXs+F23x9nu4lIwpr23OyqS5yyGwNnvjacyyJyrkuILi2qftwUl3maMJxs4c6/W82aXIdrap+blxvHg3cUv9XkuwaIHsNHiZCdMschk0o6LiyPxg7gF8/Ty6mhsT0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=dy/wyrET; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=HvY/ce1c; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="dy/wyrET"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="HvY/ce1c" Date: Fri, 02 May 2025 09:04:23 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1746176664; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hZBMg1HNimID/HjHet2qzHaStsWgjJ/gT5Tn8XOwUSM=; b=dy/wyrETpeR2P5vI0glbgJACHlGPeOWk2DciaXJftH5JdvQZjAE5RHcfHXsaZYwt9tJ+6T SW50SmDr2t6gi0UqM8JZHw+vkfiNVwKpGtLS1du/kvqboVfpdpZztxMWOiR6wYashNUg99 GwIZKp4dZ1J1JsRy6OW3spld0WU0bT0DHY/cJbvA3YdjGNou5w78I3urrG//3MYyRGJErR CG4NJAPro2e3a9BrNF15v1VQ9oWMXJrdjUsFWHQy22yklgNIxfDArYDrJyGCHrDrf9ZonC 69fKVJLkXi8GvLhsLBWgcRmY/6L2M7eBstJFB/5mVAfwcYGtPrkzQM1x5UFBjQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1746176664; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hZBMg1HNimID/HjHet2qzHaStsWgjJ/gT5Tn8XOwUSM=; b=HvY/ce1cmEDP0oVo0DUJo7EO5rl2u+vfCMaWmG8YLmHeIMsy9MRW589OAQ3dPO8GeSuosR WwghYp8+IhOn6yAA== From: "tip-bot2 for Xin Li (Intel)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/merge] x86/msr: Convert __wrmsr() uses to native_wrmsr{,q}() uses Cc: "Xin Li (Intel)" , Ingo Molnar , "Peter Zijlstra (Intel)" , Andy Lutomirski , Brian Gerst , David Woodhouse , "H. Peter Anvin" , Josh Poimboeuf , Juergen Gross , Kees Cook , Linus Torvalds , Paolo Bonzini , Sean Christopherson , Stefano Stabellini , Uros Bizjak , Vitaly Kuznetsov , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250427092027.1598740-8-xin@zytor.com> References: <20250427092027.1598740-8-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174617666309.22196.2833946430572793282.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/merge branch of tip: Commit-ID: 519be7da37b955164c59aacaee6d6ac89f4bbe15 Gitweb: https://git.kernel.org/tip/519be7da37b955164c59aacaee6d6ac89= f4bbe15 Author: Xin Li (Intel) AuthorDate: Sun, 27 Apr 2025 02:20:19 -07:00 Committer: Ingo Molnar CommitterDate: Fri, 02 May 2025 10:27:49 +02:00 x86/msr: Convert __wrmsr() uses to native_wrmsr{,q}() uses __wrmsr() is the lowest level MSR write API, with native_wrmsr() and native_wrmsrq() serving as higher-level wrappers around it: #define native_wrmsr(msr, low, high) \ __wrmsr(msr, low, high) #define native_wrmsrl(msr, val) \ __wrmsr((msr), (u32)((u64)(val)), \ (u32)((u64)(val) >> 32)) However, __wrmsr() continues to be utilized in various locations. MSR APIs are designed for different scenarios, such as native or pvops, with or without trace, and safe or non-safe. Unfortunately, the current MSR API names do not adequately reflect these factors, making it challenging to select the most appropriate API for various situations. To pave the way for improving MSR API names, convert __wrmsr() uses to native_wrmsr{,q}() to ensure consistent usage. Later, these APIs can be renamed to better reflect their implications, such as native or pvops, with or without trace, and safe or non-safe. No functional change intended. Signed-off-by: Xin Li (Intel) Signed-off-by: Ingo Molnar Acked-by: Peter Zijlstra (Intel) Cc: Andy Lutomirski Cc: Brian Gerst Cc: David Woodhouse Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Juergen Gross Cc: Kees Cook Cc: Linus Torvalds Cc: Paolo Bonzini Cc: Sean Christopherson Cc: Stefano Stabellini Cc: Uros Bizjak Cc: Vitaly Kuznetsov Link: https://lore.kernel.org/r/20250427092027.1598740-8-xin@zytor.com --- arch/x86/events/amd/brs.c | 2 +- arch/x86/include/asm/apic.h | 2 +- arch/x86/include/asm/msr.h | 6 ++++-- arch/x86/kernel/cpu/mce/core.c | 2 +- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 6 +++--- 5 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/amd/brs.c b/arch/x86/events/amd/brs.c index ec4e8a4..3f5ecfd 100644 --- a/arch/x86/events/amd/brs.c +++ b/arch/x86/events/amd/brs.c @@ -44,7 +44,7 @@ static inline unsigned int brs_to(int idx) static __always_inline void set_debug_extn_cfg(u64 val) { /* bits[4:3] must always be set to 11b */ - __wrmsr(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3, val >> 32); + native_wrmsrq(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3); } =20 static __always_inline u64 get_debug_extn_cfg(void) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 1c136f5..0174dd5 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -214,7 +214,7 @@ static inline void native_apic_msr_write(u32 reg, u32 v) =20 static inline void native_apic_msr_eoi(void) { - __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); + native_wrmsrq(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK); } =20 static inline u32 native_apic_msr_read(u32 reg) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index fbeb313..e5f95a1 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -127,10 +127,12 @@ static inline u64 native_read_msr_safe(u32 msr, int *= err) static inline void notrace native_write_msr(u32 msr, u32 low, u32 high) { - __wrmsr(msr, low, high); + u64 val =3D (u64)high << 32 | low; + + native_wrmsrq(msr, val); =20 if (tracepoint_enabled(write_msr)) - do_trace_write_msr(msr, ((u64)high << 32 | low), 0); + do_trace_write_msr(msr, val, 0); } =20 /* Can be uninlined because referenced by paravirt */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 7b9908c..96db2fd 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1306,7 +1306,7 @@ static noinstr bool mce_check_crashing_cpu(void) } =20 if (mcgstatus & MCG_STATUS_RIPV) { - __wrmsr(MSR_IA32_MCG_STATUS, 0, 0); + native_wrmsrq(MSR_IA32_MCG_STATUS, 0); return true; } } diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cp= u/resctrl/pseudo_lock.c index 61d7625..6e5edd7 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -483,7 +483,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr) * cache. */ saved_msr =3D __rdmsr(MSR_MISC_FEATURE_CONTROL); - __wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0); + native_wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); closid_p =3D this_cpu_read(pqr_state.cur_closid); rmid_p =3D this_cpu_read(pqr_state.cur_rmid); mem_r =3D plr->kmem; @@ -495,7 +495,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr) * pseudo-locked followed by reading of kernel memory to load it * into the cache. */ - __wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, plr->closid); + native_wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, plr->closid); =20 /* * Cache was flushed earlier. Now access kernel memory to read it @@ -532,7 +532,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr) * Critical section end: restore closid with capacity bitmask that * does not overlap with pseudo-locked region. */ - __wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, closid_p); + native_wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, closid_p); =20 /* Re-enable the hardware prefetcher(s) */ wrmsrq(MSR_MISC_FEATURE_CONTROL, saved_msr);