From nobody Sat Feb 7 08:53:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C186022D78B; Fri, 2 May 2025 09:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176665; cv=none; b=ncX62BD8wU7IzH4yKbFRn+C/Csnqk14/Yse+zTv0jRIzGoz/J6ej9qUzhUNTRtyN4UI0dgOWtrN3rZcK14BIcYqcHi0nain2sjr5p5rm7LGj+AKbn0mASlR0BgW/qXovUgIsSmm66IA7cAbX5w38AFw8+Kk3WZY0NOEPLWwzbuY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746176665; c=relaxed/simple; bh=QU4Co/SiX/1JUS3xdc2zSbdRe3IGb/vmTUiSYKWTkkU=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=V4jbzECcSi6svJxUM67FpCWbAUMPvomeRRx7VuGwiIN3uoeFezNlurLZpSXsu1qHsFqm37Qhx6gtrOgqcCbCiaatQRNaGiqE449tUadpPEuXO2GEF3Syt88LnCHfYLkp5A4m7YaPXJ2oUat10z/1wayD3gyQAjfcP+lJ6bVPoV0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=olF66gdB; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cEgk4C1z; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="olF66gdB"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cEgk4C1z" Date: Fri, 02 May 2025 09:04:20 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1746176660; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DX4q/oZrWYVFNYipoaEElNKiSDClpqxdvKWGsW1aKGw=; b=olF66gdBAvgjY8cNy9ogGqK4yyeY7hO8JUKgiTRjmeyxEPSqWOXhmhtZk3EiTDV/Pu9z0v R2MM6nokXlOpP2nAIKff/hviWz4ZES7fqfHY3dsgGalPrME4JtmvHyMLoBOELyUPPOxi8j ilPtj308vvrbckCIlQXZ2yICEDdsYYLk0C5fcD9MaiFmjsVJuS7nO+XVGivnCIEr9M9C0R QTIEK8+3ng7qwMvN2xoiWKIIQmNxII5N+UJIJewkaAtA7GNDYbk5flpmC0NQW9JBvbchni EXvJNdlms9XQJyxhRBMLpOEfT0HF82TuoRm4NYMPHrHR6URC8ghMZLTY5d5uaw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1746176660; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DX4q/oZrWYVFNYipoaEElNKiSDClpqxdvKWGsW1aKGw=; b=cEgk4C1z8bXVCMKI/MMDhYxymMlpDnz96iba2HhpAHEY/4uGiHLmSk4cJ4oJ0DJ4AxM5qH YnADTMoISYdPluAA== From: "tip-bot2 for Xin Li (Intel)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/merge] x86/xen/msr: Remove pmu_msr_{read,write}() Cc: "H. Peter Anvin (Intel)" , Juergen Gross , "Xin Li (Intel)" , Ingo Molnar , "Peter Zijlstra (Intel)" , Andy Lutomirski , Brian Gerst , David Woodhouse , Josh Poimboeuf , Kees Cook , Linus Torvalds , Paolo Bonzini , Sean Christopherson , Stefano Stabellini , Uros Bizjak , Vitaly Kuznetsov , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250427092027.1598740-12-xin@zytor.com> References: <20250427092027.1598740-12-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174617666013.22196.7109101589277660040.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/merge branch of tip: Commit-ID: f7998621db691b6fad4d84ad7d8ecc1a0a9b703f Gitweb: https://git.kernel.org/tip/f7998621db691b6fad4d84ad7d8ecc1a0= a9b703f Author: Xin Li (Intel) AuthorDate: Sun, 27 Apr 2025 02:20:23 -07:00 Committer: Ingo Molnar CommitterDate: Fri, 02 May 2025 10:36:35 +02:00 x86/xen/msr: Remove pmu_msr_{read,write}() As pmu_msr_{read,write}() are now wrappers of pmu_msr_chk_emulated(), remove them and use pmu_msr_chk_emulated() directly. As pmu_msr_chk_emulated() could easily return false in the cases where it would set *emul to false, remove the "emul" argument and use the return value instead. While at it, convert the data type of MSR index to u32 in functions called in pmu_msr_chk_emulated(). Suggested-by: H. Peter Anvin (Intel) Suggested-by: Juergen Gross Signed-off-by: Xin Li (Intel) Signed-off-by: Ingo Molnar Reviewed-by: Juergen Gross Acked-by: Peter Zijlstra (Intel) Cc: Andy Lutomirski Cc: Brian Gerst Cc: David Woodhouse Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Kees Cook Cc: Linus Torvalds Cc: Paolo Bonzini Cc: Sean Christopherson Cc: Stefano Stabellini Cc: Uros Bizjak Cc: Vitaly Kuznetsov Link: https://lore.kernel.org/r/20250427092027.1598740-12-xin@zytor.com --- arch/x86/xen/enlighten_pv.c | 15 ++++++++------- arch/x86/xen/pmu.c | 33 ++++++++------------------------- arch/x86/xen/xen-ops.h | 3 +-- 3 files changed, 17 insertions(+), 34 deletions(-) diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 530b59b..719370d 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1091,7 +1091,7 @@ static u64 xen_do_read_msr(unsigned int msr, int *err) { u64 val =3D 0; /* Avoid uninitialized value for safe variant. */ =20 - if (pmu_msr_read_emulated(msr, &val)) + if (pmu_msr_chk_emulated(msr, &val, true)) return val; =20 if (err) @@ -1163,12 +1163,13 @@ static void xen_do_write_msr(unsigned int msr, unsi= gned int low, default: val =3D (u64)high << 32 | low; =20 - if (!pmu_msr_write_emulated(msr, val)) { - if (err) - *err =3D native_write_msr_safe(msr, low, high); - else - native_write_msr(msr, low, high); - } + if (pmu_msr_chk_emulated(msr, &val, false)) + return; + + if (err) + *err =3D native_write_msr_safe(msr, low, high); + else + native_write_msr(msr, low, high); } } =20 diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index 0062dbb..043d72b 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -129,7 +129,7 @@ static inline uint32_t get_fam15h_addr(u32 addr) return addr; } =20 -static inline bool is_amd_pmu_msr(unsigned int msr) +static bool is_amd_pmu_msr(u32 msr) { if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD && boot_cpu_data.x86_vendor !=3D X86_VENDOR_HYGON) @@ -195,8 +195,7 @@ static bool is_intel_pmu_msr(u32 msr_index, int *type, = int *index) } } =20 -static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type, - int index, bool is_read) +static bool xen_intel_pmu_emulate(u32 msr, u64 *val, int type, int index, = bool is_read) { uint64_t *reg =3D NULL; struct xen_pmu_intel_ctxt *ctxt; @@ -258,7 +257,7 @@ static bool xen_intel_pmu_emulate(unsigned int msr, u64= *val, int type, return false; } =20 -static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read) +static bool xen_amd_pmu_emulate(u32 msr, u64 *val, bool is_read) { uint64_t *reg =3D NULL; int i, off =3D 0; @@ -299,33 +298,17 @@ static bool xen_amd_pmu_emulate(unsigned int msr, u64= *val, bool is_read) return false; } =20 -static bool pmu_msr_chk_emulated(unsigned int msr, uint64_t *val, bool is_= read, - bool *emul) +bool pmu_msr_chk_emulated(u32 msr, u64 *val, bool is_read) { int type, index =3D 0; =20 if (is_amd_pmu_msr(msr)) - *emul =3D xen_amd_pmu_emulate(msr, val, is_read); - else if (is_intel_pmu_msr(msr, &type, &index)) - *emul =3D xen_intel_pmu_emulate(msr, val, type, index, is_read); - else - return false; - - return true; -} - -bool pmu_msr_read_emulated(u32 msr, u64 *val) -{ - bool emulated; + return xen_amd_pmu_emulate(msr, val, is_read); =20 - return pmu_msr_chk_emulated(msr, val, true, &emulated) && emulated; -} + if (is_intel_pmu_msr(msr, &type, &index)) + return xen_intel_pmu_emulate(msr, val, type, index, is_read); =20 -bool pmu_msr_write_emulated(u32 msr, u64 val) -{ - bool emulated; - - return pmu_msr_chk_emulated(msr, &val, false, &emulated) && emulated; + return false; } =20 static u64 xen_amd_read_pmc(int counter) diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h index 2de3061..090349b 100644 --- a/arch/x86/xen/xen-ops.h +++ b/arch/x86/xen/xen-ops.h @@ -271,8 +271,7 @@ void xen_pmu_finish(int cpu); static inline void xen_pmu_init(int cpu) {} static inline void xen_pmu_finish(int cpu) {} #endif -bool pmu_msr_read_emulated(u32 msr, u64 *val); -bool pmu_msr_write_emulated(u32 msr, u64 val); +bool pmu_msr_chk_emulated(u32 msr, u64 *val, bool is_read); int pmu_apic_update(uint32_t reg); u64 xen_read_pmc(int counter);