From nobody Fri Dec 19 20:52:45 2025 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6B9E51D515B; Wed, 16 Apr 2025 15:36:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744817769; cv=none; b=dY1my7I+hWb9cIlNS7A6FUJuuAmAAt57gVImkshWCAOakMqtsmwStx9vvAo0YSdVQFpj/6FZABn7uSgIMO6C61PTlQD6SEI4sarlr9uGbs+CkXOIhbeyIfKV/r1rFbBcWEqQHJ9PWOptVdjjYK2GWtMJL4UaxtJZg+joMCpNJ+c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744817769; c=relaxed/simple; bh=GtSVdtZ/V1+iYr56K8Yvc3x9XkXY1q8WIepuojgDlrw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=f5eTv1jXplRhSMvLuiGMsIULthsdofWNWt4iJgpxjJDoobXHjfjx+xP/RhvFxPyXsBZMqEe32eonK56xXhB7/bgt+9kxzYvm++/c1Fv3DGzWF85CbupIJqlZ119ac/N2dlUMFKd3iqvYqeTdMhfOGf0a4rnF1qlw8LJUt2cTBQM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com; spf=pass smtp.mailfrom=linux.microsoft.com; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b=dtR/kVP1; arc=none smtp.client-ip=13.77.154.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="dtR/kVP1" Received: by linux.microsoft.com (Postfix, from userid 1134) id 12D292052501; Wed, 16 Apr 2025 08:36:08 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 12D292052501 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1744817768; bh=fPxUGRlol3w7Yog3p/+opsa8SopsGuKCNyGO7607kXU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dtR/kVP1xEXf4C7LsYu4syx8T5MELk9SoXhCGRQiMJjzA4jte8Gdjht5ov4iVbBGN hn0thBDjK+4jlM6SPgxe8+4pbMeetcnu+yDMakFB9bhMOXu2VrLDICgT7YvcMkBgzV ailmTV3YlD1VVA6LPhKdNj+jwg38g9/E9VlnaqPk= From: Shradha Gupta To: linux-hyperv@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Nipun Gupta , Yury Norov , Jason Gunthorpe , Jonathan Cameron , Anna-Maria Behnsen , Shradha Gupta , Shivamurthy Shastri , Kevin Tian , Long Li , Thomas Gleixner , Bjorn Helgaas , Rob Herring , Manivannan Sadhasivam , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Lorenzo Pieralisi , Dexuan Cui , Wei Liu , Haiyang Zhang , "K. Y. Srinivasan" , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Konstantin Taranov , Simon Horman , Leon Romanovsky , Maxim Levitsky , Erni Sri Satya Vennela , Peter Zijlstra , netdev@vger.kernel.org, linux-rdma@vger.kernel.org, Paul Rosswurm Cc: Shradha Gupta Subject: [PATCH 1/2] PCI: hv: enable pci_hyperv to allow dynamic vector allocation Date: Wed, 16 Apr 2025 08:36:06 -0700 Message-Id: <1744817766-3134-1-git-send-email-shradhagupta@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1744817747-2920-1-git-send-email-shradhagupta@linux.microsoft.com> References: <1744817747-2920-1-git-send-email-shradhagupta@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For supporting dynamic MSI vector allocation by pci controllers, enabling the flag MSI_FLAG_PCI_MSIX_ALLOC_DYN is not enough, msix_prepare_msi_desc() to prepare the desc is needed. Export pci_msix_prepare_desc() to allow pci controllers like pci-hyperv to support dynamic MSI vector allocation. Also, add the flag MSI_FLAG_PCI_MSIX_ALLOC_DYN and use pci_msix_prepare_desc() in pci_hyperv controller Signed-off-by: Shradha Gupta Reviewed-by: Haiyang Zhang Reviewed-by: Long Li --- drivers/pci/controller/pci-hyperv.c | 7 +++++-- drivers/pci/msi/irqdomain.c | 5 +++-- include/linux/msi.h | 2 ++ 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller/p= ci-hyperv.c index ac27bda5ba26..f2fa6bdb6bb8 100644 --- a/drivers/pci/controller/pci-hyperv.c +++ b/drivers/pci/controller/pci-hyperv.c @@ -598,7 +598,8 @@ static unsigned int hv_msi_get_int_vector(struct irq_da= ta *data) return cfg->vector; } =20 -#define hv_msi_prepare pci_msi_prepare +#define hv_msi_prepare pci_msi_prepare +#define hv_msix_prepare_desc pci_msix_prepare_desc =20 /** * hv_arch_irq_unmask() - "Unmask" the IRQ by setting its current @@ -727,6 +728,7 @@ static void hv_arch_irq_unmask(struct irq_data *data) #define FLOW_HANDLER NULL #define FLOW_NAME NULL #define hv_msi_prepare NULL +#define hv_msix_prepare_desc NULL =20 struct hv_pci_chip_data { DECLARE_BITMAP(spi_map, HV_PCI_MSI_SPI_NR); @@ -2063,6 +2065,7 @@ static struct irq_chip hv_msi_irq_chip =3D { static struct msi_domain_ops hv_msi_ops =3D { .msi_prepare =3D hv_msi_prepare, .msi_free =3D hv_msi_free, + .prepare_desc =3D hv_msix_prepare_desc, }; =20 /** @@ -2084,7 +2087,7 @@ static int hv_pcie_init_irq_domain(struct hv_pcibus_d= evice *hbus) hbus->msi_info.ops =3D &hv_msi_ops; hbus->msi_info.flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI | - MSI_FLAG_PCI_MSIX); + MSI_FLAG_PCI_MSIX | MSI_FLAG_PCI_MSIX_ALLOC_DYN); hbus->msi_info.handler =3D FLOW_HANDLER; hbus->msi_info.handler_name =3D FLOW_NAME; hbus->msi_info.data =3D hbus; diff --git a/drivers/pci/msi/irqdomain.c b/drivers/pci/msi/irqdomain.c index d7ba8795d60f..43129aa6d6c7 100644 --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -222,13 +222,14 @@ static void pci_irq_unmask_msix(struct irq_data *data) pci_msix_unmask(irq_data_get_msi_desc(data)); } =20 -static void pci_msix_prepare_desc(struct irq_domain *domain, msi_alloc_inf= o_t *arg, - struct msi_desc *desc) +void pci_msix_prepare_desc(struct irq_domain *domain, msi_alloc_info_t *ar= g, + struct msi_desc *desc) { /* Don't fiddle with preallocated MSI descriptors */ if (!desc->pci.mask_base) msix_prepare_msi_desc(to_pci_dev(desc->dev), desc); } +EXPORT_SYMBOL_GPL(pci_msix_prepare_desc); =20 static const struct msi_domain_template pci_msix_template =3D { .chip =3D { diff --git a/include/linux/msi.h b/include/linux/msi.h index 86e42742fd0f..d5864d5e75c2 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -691,6 +691,8 @@ struct irq_domain *pci_msi_create_irq_domain(struct fwn= ode_handle *fwnode, struct irq_domain *parent); u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *= pdev); struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev); +void pci_msix_prepare_desc(struct irq_domain *domain, msi_alloc_info_t *ar= g, + struct msi_desc *desc); #else /* CONFIG_PCI_MSI */ static inline struct irq_domain *pci_msi_get_device_domain(struct pci_dev = *pdev) { --=20 2.34.1 From nobody Fri Dec 19 20:52:45 2025 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E70921DF985; Wed, 16 Apr 2025 15:36:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="frjf8iVx" Received: by linux.microsoft.com (Postfix, from userid 1134) id 953F82052508; Wed, 16 Apr 2025 08:36:22 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 953F82052508 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1744817782; bh=c0R5u/K7Fmc1YtwZknchgHFaUeff+gQDtJr1w06pe5c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=frjf8iVxOM8E+69n85qVsMrHAMxEj9ic2UjzvxG55Vr/S+2BDTpz+/T9A18Ti+1tU PE+QqLbxm4v4ViuDYwIs91L4wUu2uRB6h0wq8EXysXn30tM9a1ZYkd9zzdXZXbIfu1 X6ums9SRokVHlY7AYClAdw4ODlsmOXt4rbYGMv+w= From: Shradha Gupta To: linux-hyperv@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Nipun Gupta , Yury Norov , Jason Gunthorpe , Jonathan Cameron , Anna-Maria Behnsen , Shradha Gupta , Shivamurthy Shastri , Kevin Tian , Long Li , Thomas Gleixner , Bjorn Helgaas , Rob Herring , Manivannan Sadhasivam , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Lorenzo Pieralisi , Dexuan Cui , Wei Liu , Haiyang Zhang , "K. Y. Srinivasan" , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Konstantin Taranov , Simon Horman , Leon Romanovsky , Maxim Levitsky , Erni Sri Satya Vennela , Peter Zijlstra , netdev@vger.kernel.org, linux-rdma@vger.kernel.org, Paul Rosswurm Cc: Shradha Gupta Subject: [PATCH 2/2] net: mana: Allow MANA driver to allocate PCI vector dynamically Date: Wed, 16 Apr 2025 08:36:21 -0700 Message-Id: <1744817781-3243-1-git-send-email-shradhagupta@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1744817747-2920-1-git-send-email-shradhagupta@linux.microsoft.com> References: <1744817747-2920-1-git-send-email-shradhagupta@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently, the MANA driver allocates pci vector statically based on MANA_MAX_NUM_QUEUES and num_online_cpus() values and in some cases ends up allocating more vectors than it needs. This is because, by this time we do not have a HW channel and do not know how many IRQs should be allocated. To avoid this, we allocate 1 IRQ vector during the creation of HWC and after getting the value supported by hardware, dynamically add the remaining vectors. Signed-off-by: Shradha Gupta Reviewed-by: Haiyang Zhang --- .../net/ethernet/microsoft/mana/gdma_main.c | 306 ++++++++++++++---- include/net/mana/gdma.h | 5 +- 2 files changed, 250 insertions(+), 61 deletions(-) diff --git a/drivers/net/ethernet/microsoft/mana/gdma_main.c b/drivers/net/= ethernet/microsoft/mana/gdma_main.c index 4ffaf7588885..3e3b5854b736 100644 --- a/drivers/net/ethernet/microsoft/mana/gdma_main.c +++ b/drivers/net/ethernet/microsoft/mana/gdma_main.c @@ -6,6 +6,9 @@ #include #include #include +#include +#include +#include =20 #include =20 @@ -80,8 +83,15 @@ static int mana_gd_query_max_resources(struct pci_dev *p= dev) return err ? err : -EPROTO; } =20 - if (gc->num_msix_usable > resp.max_msix) - gc->num_msix_usable =3D resp.max_msix; + if (!pci_msix_can_alloc_dyn(pdev)) { + if (gc->num_msix_usable > resp.max_msix) + gc->num_msix_usable =3D resp.max_msix; + } else { + /* If dynamic allocation is enabled we have already allocated + * hwc msi + */ + gc->num_msix_usable =3D min(resp.max_msix, num_online_cpus() + 1); + } =20 if (gc->num_msix_usable <=3D 1) return -ENOSPC; @@ -465,9 +475,10 @@ static int mana_gd_register_irq(struct gdma_queue *que= ue, struct gdma_irq_context *gic; struct gdma_context *gc; unsigned int msi_index; - unsigned long flags; + struct list_head *pos; + unsigned long flags, flag_irq; struct device *dev; - int err =3D 0; + int err =3D 0, count; =20 gc =3D gd->gdma_context; dev =3D gc->dev; @@ -482,7 +493,22 @@ static int mana_gd_register_irq(struct gdma_queue *que= ue, } =20 queue->eq.msix_index =3D msi_index; - gic =3D &gc->irq_contexts[msi_index]; + + /* get the msi_index value from the list*/ + count =3D 0; + spin_lock_irqsave(&gc->irq_ctxs_lock, flag_irq); + list_for_each(pos, &gc->irq_contexts) { + if (count =3D=3D msi_index) { + gic =3D list_entry(pos, struct gdma_irq_context, gic_list); + break; + } + + count++; + } + spin_unlock_irqrestore(&gc->irq_ctxs_lock, flag_irq); + + if (!gic) + return -1; =20 spin_lock_irqsave(&gic->lock, flags); list_add_rcu(&queue->entry, &gic->eq_list); @@ -497,8 +523,10 @@ static void mana_gd_deregiser_irq(struct gdma_queue *q= ueue) struct gdma_irq_context *gic; struct gdma_context *gc; unsigned int msix_index; - unsigned long flags; + struct list_head *pos; + unsigned long flags, flag_irq; struct gdma_queue *eq; + int count; =20 gc =3D gd->gdma_context; =20 @@ -507,7 +535,22 @@ static void mana_gd_deregiser_irq(struct gdma_queue *q= ueue) if (WARN_ON(msix_index >=3D gc->num_msix_usable)) return; =20 - gic =3D &gc->irq_contexts[msix_index]; + /* get the msi_index value from the list*/ + count =3D 0; + spin_lock_irqsave(&gc->irq_ctxs_lock, flag_irq); + list_for_each(pos, &gc->irq_contexts) { + if (count =3D=3D msix_index) { + gic =3D list_entry(pos, struct gdma_irq_context, gic_list); + break; + } + + count++; + } + spin_unlock_irqrestore(&gc->irq_ctxs_lock, flag_irq); + + if (!gic) + return; + spin_lock_irqsave(&gic->lock, flags); list_for_each_entry_rcu(eq, &gic->eq_list, entry) { if (queue =3D=3D eq) { @@ -1288,11 +1331,11 @@ void mana_gd_free_res_map(struct gdma_resource *r) r->size =3D 0; } =20 -static int irq_setup(unsigned int *irqs, unsigned int len, int node) +static int irq_setup(unsigned int *irqs, unsigned int len, int node, int s= kip_cpu) { const struct cpumask *next, *prev =3D cpu_none_mask; cpumask_var_t cpus __free(free_cpumask_var); - int cpu, weight; + int cpu, weight, i =3D 0; =20 if (!alloc_cpumask_var(&cpus, GFP_KERNEL)) return -ENOMEM; @@ -1303,9 +1346,21 @@ static int irq_setup(unsigned int *irqs, unsigned in= t len, int node) while (weight > 0) { cpumask_andnot(cpus, next, prev); for_each_cpu(cpu, cpus) { + /* If the call is made for irqs which are dynamically + * added and the num of vcpus is more or equal to + * allocated msix, we need to skip the first + * set of cpus, since they are already affinitized + * to HWC IRQ + */ + if (skip_cpu && !i) { + i =3D 1; + goto next_cpumask; + } if (len-- =3D=3D 0) goto done; + irq_set_affinity_and_hint(*irqs++, topology_sibling_cpumask(cpu)); +next_cpumask: cpumask_andnot(cpus, cpus, topology_sibling_cpumask(cpu)); --weight; } @@ -1317,29 +1372,92 @@ static int irq_setup(unsigned int *irqs, unsigned i= nt len, int node) return 0; } =20 -static int mana_gd_setup_irqs(struct pci_dev *pdev) +static int mana_gd_setup_dyn_irqs(struct pci_dev *pdev, int nvec) { struct gdma_context *gc =3D pci_get_drvdata(pdev); - unsigned int max_queues_per_port; struct gdma_irq_context *gic; - unsigned int max_irqs, cpu; - int start_irq_index =3D 1; - int nvec, *irqs, irq; + int *irqs, irq, skip_first_cpu =3D 0; + unsigned long flags; int err, i =3D 0, j; =20 cpus_read_lock(); - max_queues_per_port =3D num_online_cpus(); - if (max_queues_per_port > MANA_MAX_NUM_QUEUES) - max_queues_per_port =3D MANA_MAX_NUM_QUEUES; + spin_lock_irqsave(&gc->irq_ctxs_lock, flags); + irqs =3D kmalloc_array(nvec, sizeof(int), GFP_KERNEL); + if (!irqs) { + err =3D -ENOMEM; + goto free_irq_vector; + } =20 - /* Need 1 interrupt for the Hardware communication Channel (HWC) */ - max_irqs =3D max_queues_per_port + 1; + for (i =3D 0; i < nvec; i++) { + gic =3D kcalloc(1, sizeof(struct gdma_irq_context), GFP_KERNEL); + if (!gic) { + err =3D -ENOMEM; + goto free_irq; + } + gic->handler =3D mana_gd_process_eq_events; + INIT_LIST_HEAD(&gic->eq_list); + spin_lock_init(&gic->lock); =20 - nvec =3D pci_alloc_irq_vectors(pdev, 2, max_irqs, PCI_IRQ_MSIX); - if (nvec < 0) { - cpus_read_unlock(); - return nvec; + snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_q%d@pci:%s", + i, pci_name(pdev)); + + /* one pci vector is already allocated for HWC */ + irqs[i] =3D pci_irq_vector(pdev, i + 1); + if (irqs[i] < 0) { + err =3D irqs[i]; + goto free_current_gic; + } + + err =3D request_irq(irqs[i], mana_gd_intr, 0, gic->name, gic); + if (err) + goto free_current_gic; + + list_add_tail(&gic->gic_list, &gc->irq_contexts); + } + + if (gc->num_msix_usable <=3D num_online_cpus()) + skip_first_cpu =3D 1; + + err =3D irq_setup(irqs, nvec, gc->numa_node, skip_first_cpu); + if (err) + goto free_irq; + + spin_unlock_irqrestore(&gc->irq_ctxs_lock, flags); + cpus_read_unlock(); + kfree(irqs); + return 0; + +free_current_gic: + kfree(gic); +free_irq: + for (j =3D i - 1; j >=3D 0; j--) { + irq =3D pci_irq_vector(pdev, j + 1); + gic =3D list_last_entry(&gc->irq_contexts, struct gdma_irq_context, gic_= list); + irq_update_affinity_hint(irq, NULL); + free_irq(irq, gic); + list_del(&gic->gic_list); + kfree(gic); } + kfree(irqs); +free_irq_vector: + spin_unlock_irqrestore(&gc->irq_ctxs_lock, flags); + cpus_read_unlock(); + return err; +} + +static int mana_gd_setup_irqs(struct pci_dev *pdev, int nvec) +{ + struct gdma_context *gc =3D pci_get_drvdata(pdev); + struct gdma_irq_context *gic; + int start_irq_index =3D 1; + unsigned long flags; + unsigned int cpu; + int *irqs, irq; + int err, i =3D 0, j; + + cpus_read_lock(); + spin_lock_irqsave(&gc->irq_ctxs_lock, flags); + if (nvec <=3D num_online_cpus()) start_irq_index =3D 0; =20 @@ -1349,15 +1467,12 @@ static int mana_gd_setup_irqs(struct pci_dev *pdev) goto free_irq_vector; } =20 - gc->irq_contexts =3D kcalloc(nvec, sizeof(struct gdma_irq_context), - GFP_KERNEL); - if (!gc->irq_contexts) { - err =3D -ENOMEM; - goto free_irq_array; - } - for (i =3D 0; i < nvec; i++) { - gic =3D &gc->irq_contexts[i]; + gic =3D kcalloc(1, sizeof(struct gdma_irq_context), GFP_KERNEL); + if (!gic) { + err =3D -ENOMEM; + goto free_irq; + } gic->handler =3D mana_gd_process_eq_events; INIT_LIST_HEAD(&gic->eq_list); spin_lock_init(&gic->lock); @@ -1372,22 +1487,14 @@ static int mana_gd_setup_irqs(struct pci_dev *pdev) irq =3D pci_irq_vector(pdev, i); if (irq < 0) { err =3D irq; - goto free_irq; + goto free_current_gic; } =20 if (!i) { err =3D request_irq(irq, mana_gd_intr, 0, gic->name, gic); if (err) - goto free_irq; - - /* If number of IRQ is one extra than number of online CPUs, - * then we need to assign IRQ0 (hwc irq) and IRQ1 to - * same CPU. - * Else we will use different CPUs for IRQ0 and IRQ1. - * Also we are using cpumask_local_spread instead of - * cpumask_first for the node, because the node can be - * mem only. - */ + goto free_current_gic; + if (start_irq_index) { cpu =3D cpumask_local_spread(i, gc->numa_node); irq_set_affinity_and_hint(irq, cpumask_of(cpu)); @@ -1399,36 +1506,104 @@ static int mana_gd_setup_irqs(struct pci_dev *pdev) err =3D request_irq(irqs[i - start_irq_index], mana_gd_intr, 0, gic->name, gic); if (err) - goto free_irq; + goto free_current_gic; } + + list_add_tail(&gic->gic_list, &gc->irq_contexts); } =20 - err =3D irq_setup(irqs, (nvec - start_irq_index), gc->numa_node); + err =3D irq_setup(irqs, nvec - start_irq_index, gc->numa_node, 0); if (err) goto free_irq; =20 - gc->max_num_msix =3D nvec; - gc->num_msix_usable =3D nvec; + spin_unlock_irqrestore(&gc->irq_ctxs_lock, flags); cpus_read_unlock(); kfree(irqs); return 0; =20 +free_current_gic: + kfree(gic); free_irq: for (j =3D i - 1; j >=3D 0; j--) { irq =3D pci_irq_vector(pdev, j); - gic =3D &gc->irq_contexts[j]; - + gic =3D list_last_entry(&gc->irq_contexts, struct gdma_irq_context, gic_= list); irq_update_affinity_hint(irq, NULL); free_irq(irq, gic); + list_del(&gic->gic_list); + kfree(gic); } - - kfree(gc->irq_contexts); - gc->irq_contexts =3D NULL; -free_irq_array: kfree(irqs); free_irq_vector: + spin_unlock_irqrestore(&gc->irq_ctxs_lock, flags); cpus_read_unlock(); - pci_free_irq_vectors(pdev); + return err; +} + +static int mana_gd_setup_hwc_irqs(struct pci_dev *pdev) +{ + struct gdma_context *gc =3D pci_get_drvdata(pdev); + unsigned int max_irqs, min_irqs; + int max_queues_per_port; + int nvec, err; + + if (pci_msix_can_alloc_dyn(pdev)) { + max_irqs =3D 1; + min_irqs =3D 1; + } else { + max_queues_per_port =3D num_online_cpus(); + if (max_queues_per_port > MANA_MAX_NUM_QUEUES) + max_queues_per_port =3D MANA_MAX_NUM_QUEUES; + /* Need 1 interrupt for the Hardware communication Channel (HWC) */ + max_irqs =3D max_queues_per_port + 1; + min_irqs =3D 2; + } + + nvec =3D pci_alloc_irq_vectors(pdev, min_irqs, max_irqs, PCI_IRQ_MSIX); + if (nvec < 0) + return nvec; + + err =3D mana_gd_setup_irqs(pdev, nvec); + if (err) { + pci_free_irq_vectors(pdev); + return err; + } + + gc->num_msix_usable =3D nvec; + gc->max_num_msix =3D nvec; + + return err; +} + +static int mana_gd_setup_remaining_irqs(struct pci_dev *pdev) +{ + struct gdma_context *gc =3D pci_get_drvdata(pdev); + int max_irqs, i, err =3D 0; + struct msi_map irq_map; + + if (!pci_msix_can_alloc_dyn(pdev)) + /* remain irqs are already allocated with HWC IRQ */ + return 0; + + /* allocate only remaining IRQs*/ + max_irqs =3D gc->num_msix_usable - 1; + + for (i =3D 1; i <=3D max_irqs; i++) { + irq_map =3D pci_msix_alloc_irq_at(pdev, i, NULL); + if (!irq_map.virq) { + err =3D irq_map.index; + /* caller will handle cleaning up all allocated + * irqs, after HWC is destroyed + */ + return err; + } + } + + err =3D mana_gd_setup_dyn_irqs(pdev, max_irqs); + if (err) + return err; + + gc->max_num_msix =3D gc->max_num_msix + max_irqs; + return err; } =20 @@ -1436,29 +1611,34 @@ static void mana_gd_remove_irqs(struct pci_dev *pde= v) { struct gdma_context *gc =3D pci_get_drvdata(pdev); struct gdma_irq_context *gic; - int irq, i; + struct list_head *pos, *n; + unsigned long flags; + int irq, i =3D 0; =20 if (gc->max_num_msix < 1) return; =20 - for (i =3D 0; i < gc->max_num_msix; i++) { + spin_lock_irqsave(&gc->irq_ctxs_lock, flags); + list_for_each_safe(pos, n, &gc->irq_contexts) { irq =3D pci_irq_vector(pdev, i); if (irq < 0) continue; =20 - gic =3D &gc->irq_contexts[i]; + gic =3D list_entry(pos, struct gdma_irq_context, gic_list); =20 /* Need to clear the hint before free_irq */ irq_update_affinity_hint(irq, NULL); free_irq(irq, gic); + list_del(pos); + kfree(gic); + i++; } + spin_unlock_irqrestore(&gc->irq_ctxs_lock, flags); =20 pci_free_irq_vectors(pdev); =20 gc->max_num_msix =3D 0; gc->num_msix_usable =3D 0; - kfree(gc->irq_contexts); - gc->irq_contexts =3D NULL; } =20 static int mana_gd_setup(struct pci_dev *pdev) @@ -1469,9 +1649,9 @@ static int mana_gd_setup(struct pci_dev *pdev) mana_gd_init_registers(pdev); mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base); =20 - err =3D mana_gd_setup_irqs(pdev); + err =3D mana_gd_setup_hwc_irqs(pdev); if (err) { - dev_err(gc->dev, "Failed to setup IRQs: %d\n", err); + dev_err(gc->dev, "Failed to setup IRQs for HWC creation: %d\n", err); return err; } =20 @@ -1487,6 +1667,10 @@ static int mana_gd_setup(struct pci_dev *pdev) if (err) goto destroy_hwc; =20 + err =3D mana_gd_setup_remaining_irqs(pdev); + if (err) + goto destroy_hwc; + err =3D mana_gd_detect_devices(pdev); if (err) goto destroy_hwc; @@ -1563,6 +1747,8 @@ static int mana_gd_probe(struct pci_dev *pdev, const = struct pci_device_id *ent) gc->is_pf =3D mana_is_pf(pdev->device); gc->bar0_va =3D bar0_va; gc->dev =3D &pdev->dev; + INIT_LIST_HEAD(&gc->irq_contexts); + spin_lock_init(&gc->irq_ctxs_lock); =20 if (gc->is_pf) gc->mana_pci_debugfs =3D debugfs_create_dir("0", mana_debugfs_root); diff --git a/include/net/mana/gdma.h b/include/net/mana/gdma.h index 228603bf03f2..eae38d7302fe 100644 --- a/include/net/mana/gdma.h +++ b/include/net/mana/gdma.h @@ -363,6 +363,7 @@ struct gdma_irq_context { spinlock_t lock; struct list_head eq_list; char name[MANA_IRQ_NAME_SZ]; + struct list_head gic_list; }; =20 struct gdma_context { @@ -373,7 +374,9 @@ struct gdma_context { unsigned int max_num_queues; unsigned int max_num_msix; unsigned int num_msix_usable; - struct gdma_irq_context *irq_contexts; + struct list_head irq_contexts; + /* Protect the irq_contexts list */ + spinlock_t irq_ctxs_lock; =20 /* L2 MTU */ u16 adapter_mtu; --=20 2.34.1