From nobody Fri Dec 19 14:23:28 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACEAF1FDD; Mon, 14 Apr 2025 15:25:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744644336; cv=none; b=jA0i2nAjsh0KNysu1ugiznqxSIwOAX2Gq1je6MrSeneOl83I3O1IgSc8YVed2M6iBA19/CLC+R/eO5Rkz9OTuS3m/Yruzwr6OpcOaQ9PLOZmXGJoennnACq3cd0wZs+d5b/xtdTEyc/aXN7vAB2vZaJmEnuk8UZNwTXesJmHFsg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744644336; c=relaxed/simple; bh=y6yz8eG3xQ0fyYP9YIopaUmz0nDdVPc/Jh3OkNzxgjk=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=UEWwZzQyR1tFE+xylTBL1ghu+JZjz+ex2nszbXBej9SRonhsW+xXiEMiR1tS7CZs8IBj1TThomGSDUkJfFsw2FwQ3rkarLtTDvocsKhhZS7M+OVEA8R73X+1hOV3rAWjlP13808kvz5798LGhBXoGcwtDSvv3zXMovmHMr+PhjY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=WppRh4Bd; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=LFX7jvGf; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="WppRh4Bd"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="LFX7jvGf" Date: Mon, 14 Apr 2025 15:25:20 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1744644326; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3qJxCJxTPme5lnrRdpPFvQmpJRRGWDgVC5HggM5lAIE=; b=WppRh4Bdcs2YKhzvuWoHWv1Bq+DEFjc392xHciOstQHmnZ44+swFS93hrdYG4k4/Z/qRd1 0zfDbrmq2vWuDVWD9dD95Ov+lLTCmY5ptFxznJyCntBfHDTi0R02u9umUZO2pASk3VLigK sF9ZLuJryidUut5YDBbcALq3PnaW2uII6fHZv/VjGrficuEr0HS4Ebq2n6E4w63zELZGi/ 37cANqgmdf/1UXv9jgwH22Auua50x/qf23+sT5D3EGTC9r/FkL65fhsJkMHFcArYzUPTTM 5K0CEJVhKZEKH9zOb8Yea+JslpjQLwOjlo9YVKRFbiZAqDxyheI8cpBRI9pTmw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1744644326; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3qJxCJxTPme5lnrRdpPFvQmpJRRGWDgVC5HggM5lAIE=; b=LFX7jvGf+DmdoHdPHCQSgdHct1yrwcil80yr/K3JMjqdvQalNpBviaNdHin4cEabEuof0H N0wRcAYk6yhguxAg== From: "tip-bot2 for Borislav Petkov (AMD)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] x86/bugs: Remove X86_BUG_MMIO_UNKNOWN Cc: "Borislav Petkov (AMD)" , Ingo Molnar , Andrew Cooper , David Kaplan , "H. Peter Anvin" , Josh Poimboeuf , Pawan Gupta , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250414150951.5345-1-bp@kernel.org> References: <20250414150951.5345-1-bp@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174464432010.31282.9076437983406164205.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cpu branch of tip: Commit-ID: dd86a1d013e0c94fedd060514b9e7be2988ef320 Gitweb: https://git.kernel.org/tip/dd86a1d013e0c94fedd060514b9e7be29= 88ef320 Author: Borislav Petkov (AMD) AuthorDate: Mon, 14 Apr 2025 17:09:51 +02:00 Committer: Ingo Molnar CommitterDate: Mon, 14 Apr 2025 17:15:27 +02:00 x86/bugs: Remove X86_BUG_MMIO_UNKNOWN Whack this thing because: - the "unknown" handling is done only for this vuln and not for the others - it doesn't do anything besides reporting things differently. It doesn't apply any mitigations - it is simply causing unnecessary complications to the code which don't bring anything besides maintenance overhead to what is already a very nasty spaghetti pile - all the currently unaffected CPUs can also be in "unknown" status so there's no need for special handling here so get rid of it. Signed-off-by: Borislav Petkov (AMD) Signed-off-by: Ingo Molnar Cc: Andrew Cooper Cc: David Kaplan Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Pawan Gupta Link: https://lore.kernel.org/r/20250414150951.5345-1-bp@kernel.org --- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/bugs.c | 12 +----------- arch/x86/kernel/cpu/common.c | 5 ----- tools/arch/x86/include/asm/cpufeatures.h | 2 +- 4 files changed, 3 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 6c2c152..e8f8d43 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -519,7 +519,7 @@ #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* "itlb_multihit" CPU may incu= r MCE during certain page attribute changes */ #define X86_BUG_SRBDS X86_BUG(24) /* "srbds" CPU may leak RNG bits if no= t mitigated */ #define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* "mmio_stale_data" CPU is a= ffected by Processor MMIO Stale Data vulnerabilities */ -#define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* "mmio_unknown" CPU is too old= and its MMIO Stale Data status is unknown */ +/* unused, was #define X86_BUG_MMIO_UNKNOWN X86_BUG(26) "mmio_unknown" CP= U is too old and its MMIO Stale Data status is unknown */ #define X86_BUG_RETBLEED X86_BUG(27) /* "retbleed" CPU is affected by RET= Bleed */ #define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* "eibrs_pbrsb" EIBRS is vulnera= ble to Post Barrier RSB Predictions */ #define X86_BUG_SMT_RSB X86_BUG(29) /* "smt_rsb" CPU is vulnerable to Cr= oss-Thread Return Address Predictions */ diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 4386aa6..a91a1ca 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -428,7 +428,6 @@ static const char * const mmio_strings[] =3D { static void __init mmio_select_mitigation(void) { if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) || - boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) || cpu_mitigations_off()) { mmio_mitigation =3D MMIO_MITIGATION_OFF; return; @@ -591,8 +590,6 @@ out: pr_info("TAA: %s\n", taa_strings[taa_mitigation]); if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]); - else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN)) - pr_info("MMIO Stale Data: Unknown: No mitigations\n"); if (boot_cpu_has_bug(X86_BUG_RFDS)) pr_info("Register File Data Sampling: %s\n", rfds_strings[rfds_mitigatio= n]); } @@ -2819,9 +2816,6 @@ static ssize_t tsx_async_abort_show_state(char *buf) =20 static ssize_t mmio_stale_data_show_state(char *buf) { - if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN)) - return sysfs_emit(buf, "Unknown: No mitigations\n"); - if (mmio_mitigation =3D=3D MMIO_MITIGATION_OFF) return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]); =20 @@ -3006,7 +3000,6 @@ static ssize_t cpu_show_common(struct device *dev, st= ruct device_attribute *attr return srbds_show_state(buf); =20 case X86_BUG_MMIO_STALE_DATA: - case X86_BUG_MMIO_UNKNOWN: return mmio_stale_data_show_state(buf); =20 case X86_BUG_RETBLEED: @@ -3075,10 +3068,7 @@ ssize_t cpu_show_srbds(struct device *dev, struct de= vice_attribute *attr, char * =20 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribu= te *attr, char *buf) { - if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN)) - return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN); - else - return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA); + return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA); } =20 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *att= r, char *buf) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 12126ad..4ada55f 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1402,15 +1402,10 @@ static void __init cpu_set_bug_bits(struct cpuinfo_= x86 *c) * Affected CPU list is generally enough to enumerate the vulnerability, * but for virtualization case check for ARCH_CAP MSR bits also, VMM may * not want the guest to enumerate the bug. - * - * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist, - * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits. */ if (!arch_cap_mmio_immune(x86_arch_cap_msr)) { if (cpu_matches(cpu_vuln_blacklist, MMIO)) setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); - else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO)) - setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN); } =20 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index 9e3fa79..e88500d 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -508,7 +508,7 @@ #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* "itlb_multihit" CPU may incu= r MCE during certain page attribute changes */ #define X86_BUG_SRBDS X86_BUG(24) /* "srbds" CPU may leak RNG bits if no= t mitigated */ #define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* "mmio_stale_data" CPU is a= ffected by Processor MMIO Stale Data vulnerabilities */ -#define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* "mmio_unknown" CPU is too old= and its MMIO Stale Data status is unknown */ +/* unused, was #define X86_BUG_MMIO_UNKNOWN X86_BUG(26) * "mmio_unknown" = CPU is too old and its MMIO Stale Data status is unknown */ #define X86_BUG_RETBLEED X86_BUG(27) /* "retbleed" CPU is affected by RET= Bleed */ #define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* "eibrs_pbrsb" EIBRS is vulnera= ble to Post Barrier RSB Predictions */ #define X86_BUG_SMT_RSB X86_BUG(29) /* "smt_rsb" CPU is vulnerable to Cr= oss-Thread Return Address Predictions */