From nobody Fri Dec 19 12:50:31 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DC5D1A9B48; Mon, 14 Apr 2025 07:34:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744616088; cv=none; b=t/CTvufDZ+NIRp9NJHj6cMsSKq6J3lxuvGEuD/+Gjc5S8A0mH0mngVvE5/EaaOMcbRK2mpRL4Up3JthEfkCk3HmDnkwyNwQpqVkD41VcdSCOAg3R4zmWzU1H16CPfn0kfmqYuK4O+qbZPBo4pFS58vPHp5qDhvTNIKFRPGsj7Dw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744616088; c=relaxed/simple; bh=Gxacf4xkja30r9wEhfJHDgpURZ5RU8J6eicOyu53qUU=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=EUZa074V/ZSvOfJ9Fdi+ASI59b9QTjuRa9n8/3faIfB5fyAsbabUKkQG75vYia706fy5nFjUeG9iBdrP2jqZAUo4BzhA430tXnbOS9f1FMwdAn6Nm0tebDG3XnjVi3gdzXbEkolDIAGvSepQ0JJuSQnz7b3T2+IIrD1X0BwhJGU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=j2wlqbRl; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=zVVS83hq; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="j2wlqbRl"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="zVVS83hq" Date: Mon, 14 Apr 2025 07:34:44 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1744616085; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RmSWBS2CdtsSZbF6WtFAfQCWuHUzYQ+Uqtfsdeffeok=; b=j2wlqbRlSuh52//5Pctgpx7kEgrXKUQdkCa1nPXZZOBtFt2lL6VWwQOF9I2WEvy7snkzsS Ok91m3F6+hEISNgshGkmjFZiwDmzC+WhNx5vhm877LgjdsNw3a7BZULGPVfE3LVCYSDriC XhJ0p0EHGorpUgXCUgePql/6cSTPPwRpBjLCyhcivwlkwFCiPpas2ePmqyGPefqZnlUtri aH3IGvtHy+afPGoHxUnJ9GoPR51pksEY0jslAS7L/BGPXsWTX1+Lc23+KLMI5BcikHUxAA aT8iXM3BKvVKPMu7HHlstTv53+q9CcRcqP+JdimzAleFxxYRedEu2dTFN/K9/Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1744616085; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RmSWBS2CdtsSZbF6WtFAfQCWuHUzYQ+Uqtfsdeffeok=; b=zVVS83hqblvbtDRP56tQ5xLTHWQ3EW1h3LJkZT8fR+okZ0pxuCRiQa4ZgNMqHNlVCQWfks NaeRC/Qc7+MzbfDw== From: "tip-bot2 for Ingo Molnar" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/merge] x86/fpu: Clarify FPU context cacheline alignment Cc: Peter Zijlstra , Ingo Molnar , Andy Lutomirski , "Chang S. Bae" , Fenghua Yu , "H. Peter Anvin" , Linus Torvalds , Oleg Nesterov , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174461608473.31282.14719684727200198339.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/merge branch of tip: Commit-ID: e3a52b67f54aa36ab21265eeea016460b5fe1c46 Gitweb: https://git.kernel.org/tip/e3a52b67f54aa36ab21265eeea016460b= 5fe1c46 Author: Ingo Molnar AuthorDate: Thu, 10 Apr 2025 12:52:16 +02:00 Committer: Ingo Molnar CommitterDate: Mon, 14 Apr 2025 08:18:29 +02:00 x86/fpu: Clarify FPU context cacheline alignment Suggested-by: Peter Zijlstra Signed-off-by: Ingo Molnar Cc: Andy Lutomirski Cc: Chang S. Bae Cc: Fenghua Yu Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Oleg Nesterov Link: https://lore.kernel.org/r/Z_ejggklB5-IWB5W@gmail.com --- arch/x86/kernel/fpu/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index d0a45f6..3a19877 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -607,7 +607,8 @@ int fpu_clone(struct task_struct *dst, unsigned long cl= one_flags, bool minimal, * We allocate the new FPU structure right after the end of the task stru= ct. * task allocation size already took this into account. * - * This is safe because task_struct size is a multiple of cacheline size. + * This is safe because task_struct size is a multiple of cacheline size, + * thus x86_task_fpu() will always be cacheline aligned as well. */ struct fpu *dst_fpu =3D (void *)dst + sizeof(*dst);