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Darwish" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] x86/cacheinfo: Properly parse CPUID(0x80000005) L1d/L1i associativity Cc: "Ahmed S. Darwish" , Ingo Molnar , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86-cpuid@lists.linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250409122233.1058601-2-darwi@linutronix.de> References: <20250409122233.1058601-2-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174422761402.31282.13417527364559338124.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cpu branch of tip: Commit-ID: d274cde0dbe0217ee2f2ddbb1a3c545dedf81a06 Gitweb: https://git.kernel.org/tip/d274cde0dbe0217ee2f2ddbb1a3c545de= df81a06 Author: Ahmed S. Darwish AuthorDate: Wed, 09 Apr 2025 14:22:30 +02:00 Committer: Ingo Molnar CommitterDate: Wed, 09 Apr 2025 20:47:05 +02:00 x86/cacheinfo: Properly parse CPUID(0x80000005) L1d/L1i associativity For the AMD CPUID(4) emulation cache info logic, the same associativity mapping array, assocs[], is used for both CPUID(0x80000005) and CPUID(0x80000006). This is incorrect since per the AMD manuals, the mappings for CPUID(0x80000005) L1d/L1i associativity is: n =3D 0x1 -> 0xfe n n =3D 0xff fully associative while assocs[] maps these values to: n =3D 0x1, 0x2, 0x4 n n =3D 0x3, 0x7, 0x9 0 n =3D 0x6 8 n =3D 0x8 16 n =3D 0xa 32 n =3D 0xb 48 n =3D 0xc 64 n =3D 0xd 96 n =3D 0xe 128 n =3D 0xf fully associative which is only valid for CPUID(0x80000006). Parse CPUID(0x80000005) L1d/L1i associativity values as shown in the AMD manuals. Since the 0xffff literal is used to denote full associativity at the AMD CPUID(4)-emulation logic, define AMD_CPUID4_FULLY_ASSOCIATIVE for it instead of spreading that literal in more places. Mark the assocs[] mapping array as only valid for CPUID(0x80000006) L2/L3 cache information. Fixes: a326e948c538 ("x86, cacheinfo: Fixup L3 cache information for AMD mu= lti-node processors") Signed-off-by: Ahmed S. Darwish Signed-off-by: Ingo Molnar Cc: Andrew Cooper Cc: "H. Peter Anvin" Cc: John Ogness Cc: x86-cpuid@lists.linux.dev Link: https://lore.kernel.org/r/20250409122233.1058601-2-darwi@linutronix.de --- arch/x86/kernel/cpu/cacheinfo.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index cd48d34..f4817cd 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -91,6 +91,8 @@ static const enum cache_type cache_type_map[] =3D { * AMD CPUs with TOPOEXT can just use CPUID(0x8000001d) */ =20 +#define AMD_CPUID4_FULLY_ASSOCIATIVE 0xffff + union l1_cache { struct { unsigned line_size :8; @@ -122,6 +124,7 @@ union l3_cache { unsigned int val; }; =20 +/* L2/L3 associativity mapping */ static const unsigned short assocs[] =3D { [1] =3D 1, [2] =3D 2, @@ -133,7 +136,7 @@ static const unsigned short assocs[] =3D { [0xc] =3D 64, [0xd] =3D 96, [0xe] =3D 128, - [0xf] =3D 0xffff /* Fully associative */ + [0xf] =3D AMD_CPUID4_FULLY_ASSOCIATIVE }; =20 static const unsigned char levels[] =3D { 1, 1, 2, 3 }; @@ -163,7 +166,7 @@ static void legacy_amd_cpuid4(int index, union _cpuid4_= leaf_eax *eax, if (!l1->val) return; =20 - assoc =3D assocs[l1->assoc]; + assoc =3D (l1->assoc =3D=3D 0xff) ? AMD_CPUID4_FULLY_ASSOCIATIVE : l1->= assoc; line_size =3D l1->line_size; lines_per_tag =3D l1->lines_per_tag; size_in_kb =3D l1->size_in_kb; @@ -201,7 +204,7 @@ static void legacy_amd_cpuid4(int index, union _cpuid4_= leaf_eax *eax, eax->split.num_threads_sharing =3D 0; eax->split.num_cores_on_die =3D topology_num_cores_per_package(); =20 - if (assoc =3D=3D 0xffff) + if (assoc =3D=3D AMD_CPUID4_FULLY_ASSOCIATIVE) eax->split.is_fully_associative =3D 1; =20 ebx->split.coherency_line_size =3D line_size - 1;