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Tue, 8 Apr 2025 07:02:19 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch , Vlad Dogaru , Yevgeny Kliteynik Subject: [PATCH net-next 05/12] net/mlx5: HWS, Cleanup after pool refactoring Date: Tue, 8 Apr 2025 17:00:49 +0300 Message-ID: <1744120856-341328-6-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1744120856-341328-1-git-send-email-tariqt@nvidia.com> References: <1744120856-341328-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004681:EE_|CH3PR12MB8484:EE_ X-MS-Office365-Filtering-Correlation-Id: 7bcf48e3-67ef-44c2-8a58-08dd76a6090b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?nnVAD3oSbk2BJYIJ2QqhusMs7NwCwNTZlHzTuUrfOYpfIsuJQffIDDYgK7/J?= =?us-ascii?Q?Tiyrig5bMcAVdPfjenFhDgvrhYAgVCA2/17LblLqdMIc+KXydObSGd5yBmnU?= =?us-ascii?Q?KmS2P4AWOe63P2l4+Zrxjf7z4cMTZe+64N1CzSwKi+h0R1VjmxZPbZMvsu1n?= =?us-ascii?Q?EC1qkCLxrNUSUVyDW6lNCnzL8dv6SIFdrrXxMvNGYR+u/XOtZQMI1QStfcBK?= =?us-ascii?Q?8EjTo4FLIepuhM4z4d9ZV+/NBWYFszE4h19m2nmaKPrCv5o+Bok/XzpZHCyK?= =?us-ascii?Q?GEcHbOXxDjwWtCAK7jQGIfg1qJwvCrYpZEo4h5bpps5Alazeofot2d7xvZ6f?= =?us-ascii?Q?Iytn/OBYMr3iBoi/+O0pzOLLb1mLIQPX6Zzu6jtaQle0uuRcxwkpNaTEt6Ub?= =?us-ascii?Q?rtmcA4/9hCHzW1nF02piHEl/0RbCPbOh96UGQZGJnywn48+V194zogeZfK3m?= =?us-ascii?Q?EetxxiAQG6q2v28mEx0y4guCsL1wdBT4yHaAdPFyqM76dhDMsb3EgBro25x/?= =?us-ascii?Q?Fn05DLcXva9bduFn2NRiRpCiBAJ3Tx5XPtKiVCNSCI0uXuvuP9YCesuQaQ7E?= =?us-ascii?Q?oReKJ4dKCQl9fej9qPT+/0zb9gYVmLUYr4aMelAajKu0+qVBa8MHNdKk/YZF?= =?us-ascii?Q?qpRCdjWRh/TSBMD9FGdPPUp89V0WNnk5UK3HgH7ZbffBSC0gJcqoSjHZFaXN?= =?us-ascii?Q?fK93Uq9IXqu4xggrqT8WUg7Sn5sBO50EZGOsrEmoWcOewUZ3k5ZFenR1Ykk0?= =?us-ascii?Q?m/JvyJDR52A1MR6g2Gq9PLePAXrG57UVYeliUxqAqPeI9HmdPu2wHJZkT+Xy?= =?us-ascii?Q?7nxZUBClWS/BUzF1kfptezpHLrkJPWsv4Qvs8r8D5bEuqovyNh4sCtRKgIcf?= =?us-ascii?Q?iEBxRPnmTcah2dudcERGIRJ4q2l9EVvmulRIZWUtJg7IBLE6NlixEInVtlqT?= =?us-ascii?Q?fCvBpEFAat6CG584mhX5G2SXlOz49PAzYgenFo1DZtrU8Ofw1wUsIEdc0aVO?= =?us-ascii?Q?5rbyfSTurPeVmQZmnXYFYKomStirumBOBerAxkQznH9kiyFLBXRxjCYRTSOT?= =?us-ascii?Q?CFJl9kgcAxJtDxulCNdFNDolAS/QkDfyW2PEpY4jGB2zRm9HIlGdos08iDao?= =?us-ascii?Q?HI/YGZMIQ1+f6nhDmuGNTf8KdMv6O6hNFoQmwYFELyiJ7EMHJG7r8EpyWd8Z?= =?us-ascii?Q?7Z7Jw8OvXtnQv7drY9OeFwcGaLVrlQxeK8YcPT6plsHd0o70dpGfUujIzDAY?= =?us-ascii?Q?XtH9OuEL+niiqy5m1V24CfIfsxSUvY/P5wEZcSMSzTAAcDnn5Ju06aq+n4Q2?= =?us-ascii?Q?FV7ObM7haAkAhJealJcn6Z9J7CIs7V3WOpTXT7WXPX09jLBfx0iZbFW2sjdp?= =?us-ascii?Q?2yJbDwCn6Yb06f177/EKrdjr3xbde06RKgKJrBcN9oFjJvDROhgiMvG+NaCO?= =?us-ascii?Q?c6uiBjXIR2yGEwMMHymfThDgt+HjCXhz0qn+Jdemhoaw11p6ZsJOZBbIFCvo?= =?us-ascii?Q?ttbar4+LyQGy6Cg=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2025 14:02:44.3159 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7bcf48e3-67ef-44c2-8a58-08dd76a6090b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004681.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8484 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Vlad Dogaru Remove members which are now no longer used. In fact, many of the `struct mlx5hws_pool_chunk` were not even written to beyond being initialized, but they were used in various internals. Also cleanup some local variables which made more sense when the API was thicker. Signed-off-by: Vlad Dogaru Reviewed-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/action.c | 6 +-- .../mellanox/mlx5/core/steering/hws/matcher.c | 48 ++++++------------- .../mellanox/mlx5/core/steering/hws/matcher.h | 2 - 3 files changed, 16 insertions(+), 40 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c = b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c index 39904b337b81..44b4640b47db 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c @@ -1583,7 +1583,6 @@ hws_action_create_dest_match_range_table(struct mlx5h= ws_context *ctx, struct mlx5hws_matcher_action_ste *table_ste; struct mlx5hws_pool_attr pool_attr =3D {0}; struct mlx5hws_pool *ste_pool, *stc_pool; - struct mlx5hws_pool_chunk *ste; u32 *rtc_0_id, *rtc_1_id; u32 obj_id; int ret; @@ -1613,8 +1612,6 @@ hws_action_create_dest_match_range_table(struct mlx5h= ws_context *ctx, rtc_0_id =3D &table_ste->rtc_0_id; rtc_1_id =3D &table_ste->rtc_1_id; ste_pool =3D table_ste->pool; - ste =3D &table_ste->ste; - ste->order =3D 1; =20 rtc_attr.log_size =3D 0; rtc_attr.log_depth =3D 0; @@ -1630,7 +1627,7 @@ hws_action_create_dest_match_range_table(struct mlx5h= ws_context *ctx, =20 rtc_attr.pd =3D ctx->pd_num; rtc_attr.ste_base =3D obj_id; - rtc_attr.ste_offset =3D ste->offset; + rtc_attr.ste_offset =3D 0; rtc_attr.reparse_mode =3D mlx5hws_context_get_reparse_mode(ctx); rtc_attr.table_type =3D mlx5hws_table_get_res_fw_ft_type(MLX5HWS_TABLE_TY= PE_FDB, false); =20 @@ -1833,7 +1830,6 @@ mlx5hws_action_create_dest_match_range(struct mlx5hws= _context *ctx, stc_attr.action_offset =3D MLX5HWS_ACTION_OFFSET_HIT; stc_attr.action_type =3D MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_STE_TABLE; stc_attr.reparse_mode =3D MLX5_IFC_STC_REPARSE_IGNORE; - stc_attr.ste_table.ste =3D table_ste->ste; stc_attr.ste_table.ste_pool =3D table_ste->pool; stc_attr.ste_table.match_definer_id =3D ctx->caps->trivial_match_definer; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c index 95d31fd6c976..54dd5433a3ca 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c @@ -197,22 +197,15 @@ static int hws_matcher_disconnect(struct mlx5hws_matc= her *matcher) =20 static void hws_matcher_set_rtc_attr_sz(struct mlx5hws_matcher *matcher, struct mlx5hws_cmd_rtc_create_attr *rtc_attr, - enum mlx5hws_matcher_rtc_type rtc_type, bool is_mirror) { - struct mlx5hws_pool_chunk *ste =3D &matcher->action_ste.ste; enum mlx5hws_matcher_flow_src flow_src =3D matcher->attr.optimize_flow_sr= c; - bool is_match_rtc =3D rtc_type =3D=3D HWS_MATCHER_RTC_TYPE_MATCH; =20 if ((flow_src =3D=3D MLX5HWS_MATCHER_FLOW_SRC_VPORT && !is_mirror) || (flow_src =3D=3D MLX5HWS_MATCHER_FLOW_SRC_WIRE && is_mirror)) { /* Optimize FDB RTC */ rtc_attr->log_size =3D 0; rtc_attr->log_depth =3D 0; - } else { - /* Keep original values */ - rtc_attr->log_size =3D is_match_rtc ? matcher->attr.table.sz_row_log : s= te->order; - rtc_attr->log_depth =3D is_match_rtc ? matcher->attr.table.sz_col_log : = 0; } } =20 @@ -225,8 +218,7 @@ static int hws_matcher_create_rtc(struct mlx5hws_matche= r *matcher, struct mlx5hws_context *ctx =3D matcher->tbl->ctx; struct mlx5hws_matcher_action_ste *action_ste; struct mlx5hws_table *tbl =3D matcher->tbl; - struct mlx5hws_pool *ste_pool, *stc_pool; - struct mlx5hws_pool_chunk *ste; + struct mlx5hws_pool *ste_pool; u32 *rtc_0_id, *rtc_1_id; u32 obj_id; int ret; @@ -236,8 +228,6 @@ static int hws_matcher_create_rtc(struct mlx5hws_matche= r *matcher, rtc_0_id =3D &matcher->match_ste.rtc_0_id; rtc_1_id =3D &matcher->match_ste.rtc_1_id; ste_pool =3D matcher->match_ste.pool; - ste =3D &matcher->match_ste.ste; - ste->order =3D attr->table.sz_col_log + attr->table.sz_row_log; =20 rtc_attr.log_size =3D attr->table.sz_row_log; rtc_attr.log_depth =3D attr->table.sz_col_log; @@ -273,16 +263,15 @@ static int hws_matcher_create_rtc(struct mlx5hws_matc= her *matcher, rtc_0_id =3D &action_ste->rtc_0_id; rtc_1_id =3D &action_ste->rtc_1_id; ste_pool =3D action_ste->pool; - ste =3D &action_ste->ste; /* Action RTC size calculation: * log((max number of rules in matcher) * * (max number of action STEs per rule) * * (2 to support writing new STEs for update rule)) */ - ste->order =3D ilog2(roundup_pow_of_two(action_ste->max_stes)) + - attr->table.sz_row_log + - MLX5HWS_MATCHER_ACTION_RTC_UPDATE_MULT; - rtc_attr.log_size =3D ste->order; + rtc_attr.log_size =3D + ilog2(roundup_pow_of_two(action_ste->max_stes)) + + attr->table.sz_row_log + + MLX5HWS_MATCHER_ACTION_RTC_UPDATE_MULT; rtc_attr.log_depth =3D 0; rtc_attr.update_index_mode =3D MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET; /* The action STEs use the default always hit definer */ @@ -300,21 +289,20 @@ static int hws_matcher_create_rtc(struct mlx5hws_matc= her *matcher, =20 rtc_attr.pd =3D ctx->pd_num; rtc_attr.ste_base =3D obj_id; - rtc_attr.ste_offset =3D ste->offset; + rtc_attr.ste_offset =3D 0; rtc_attr.reparse_mode =3D mlx5hws_context_get_reparse_mode(ctx); rtc_attr.table_type =3D mlx5hws_table_get_res_fw_ft_type(tbl->type, false= ); - hws_matcher_set_rtc_attr_sz(matcher, &rtc_attr, rtc_type, false); + hws_matcher_set_rtc_attr_sz(matcher, &rtc_attr, false); =20 /* STC is a single resource (obj_id), use any STC for the ID */ - stc_pool =3D ctx->stc_pool; - obj_id =3D mlx5hws_pool_get_base_id(stc_pool); + obj_id =3D mlx5hws_pool_get_base_id(ctx->stc_pool); rtc_attr.stc_base =3D obj_id; =20 ret =3D mlx5hws_cmd_rtc_create(ctx->mdev, &rtc_attr, rtc_0_id); if (ret) { mlx5hws_err(ctx, "Failed to create matcher RTC of type %s", hws_matcher_rtc_type_to_str(rtc_type)); - goto free_ste; + return ret; } =20 if (tbl->type =3D=3D MLX5HWS_TABLE_TYPE_FDB) { @@ -322,9 +310,9 @@ static int hws_matcher_create_rtc(struct mlx5hws_matche= r *matcher, rtc_attr.ste_base =3D obj_id; rtc_attr.table_type =3D mlx5hws_table_get_res_fw_ft_type(tbl->type, true= ); =20 - obj_id =3D mlx5hws_pool_get_base_mirror_id(stc_pool); + obj_id =3D mlx5hws_pool_get_base_mirror_id(ctx->stc_pool); rtc_attr.stc_base =3D obj_id; - hws_matcher_set_rtc_attr_sz(matcher, &rtc_attr, rtc_type, true); + hws_matcher_set_rtc_attr_sz(matcher, &rtc_attr, true); =20 ret =3D mlx5hws_cmd_rtc_create(ctx->mdev, &rtc_attr, rtc_1_id); if (ret) { @@ -338,16 +326,12 @@ static int hws_matcher_create_rtc(struct mlx5hws_matc= her *matcher, =20 destroy_rtc_0: mlx5hws_cmd_rtc_destroy(ctx->mdev, *rtc_0_id); -free_ste: - if (rtc_type =3D=3D HWS_MATCHER_RTC_TYPE_MATCH) - mlx5hws_pool_chunk_free(ste_pool, ste); return ret; } =20 static void hws_matcher_destroy_rtc(struct mlx5hws_matcher *matcher, enum mlx5hws_matcher_rtc_type rtc_type) { - struct mlx5hws_matcher_action_ste *action_ste; struct mlx5hws_table *tbl =3D matcher->tbl; u32 rtc_0_id, rtc_1_id; =20 @@ -357,18 +341,17 @@ static void hws_matcher_destroy_rtc(struct mlx5hws_ma= tcher *matcher, rtc_1_id =3D matcher->match_ste.rtc_1_id; break; case HWS_MATCHER_RTC_TYPE_STE_ARRAY: - action_ste =3D &matcher->action_ste; - rtc_0_id =3D action_ste->rtc_0_id; - rtc_1_id =3D action_ste->rtc_1_id; + rtc_0_id =3D matcher->action_ste.rtc_0_id; + rtc_1_id =3D matcher->action_ste.rtc_1_id; break; default: return; } =20 if (tbl->type =3D=3D MLX5HWS_TABLE_TYPE_FDB) - mlx5hws_cmd_rtc_destroy(matcher->tbl->ctx->mdev, rtc_1_id); + mlx5hws_cmd_rtc_destroy(tbl->ctx->mdev, rtc_1_id); =20 - mlx5hws_cmd_rtc_destroy(matcher->tbl->ctx->mdev, rtc_0_id); + mlx5hws_cmd_rtc_destroy(tbl->ctx->mdev, rtc_0_id); } =20 static int @@ -564,7 +547,6 @@ static int hws_matcher_bind_at(struct mlx5hws_matcher *= matcher) stc_attr.action_offset =3D MLX5HWS_ACTION_OFFSET_HIT; stc_attr.action_type =3D MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_STE_TABLE; stc_attr.reparse_mode =3D MLX5_IFC_STC_REPARSE_IGNORE; - stc_attr.ste_table.ste =3D action_ste->ste; stc_attr.ste_table.ste_pool =3D action_ste->pool; stc_attr.ste_table.match_definer_id =3D ctx->caps->trivial_match_definer; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h index 20b32012c418..0450b6175ac9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h @@ -45,14 +45,12 @@ struct mlx5hws_match_template { }; =20 struct mlx5hws_matcher_match_ste { - struct mlx5hws_pool_chunk ste; u32 rtc_0_id; u32 rtc_1_id; struct mlx5hws_pool *pool; }; =20 struct mlx5hws_matcher_action_ste { - struct mlx5hws_pool_chunk ste; struct mlx5hws_pool_chunk stc; u32 rtc_0_id; u32 rtc_1_id; --=20 2.31.1