From nobody Thu Dec 18 15:12:25 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00240261377; Wed, 19 Mar 2025 11:04:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742382248; cv=none; b=tvID0l7p63FFU4LT/gTBmUluO/YDJYqqLhsC//7IjUlNJvrDyACrsmpXH4Jb37xdB0l4OpDs+9QNZ9PEpPDTwLPpRj5aalwGilyrzVqOxQ8Ey20ej3jBSWcTwV9m4shS6fy//3/RqGacBtcd7Kjta4Xo/M7itGppjBF4KaEFnb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742382248; c=relaxed/simple; bh=o8AUVv9elK9MjDta/aXsLDCUleWMJ6/zkUprnm3zn4g=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=JHvXD1XG5z0dBFuUGHFll8n+AMy9xnc/t1OX3VZGNsUSlqZoCnuhb6txtg0Km+f0juYZz9pLO/WkLUlcmJn/gj+296G4iF/cxWlSTjyX2pdY+1Xtskcpn+xhyNlLbLpuLWSEblXU67q4xHQXrWiwOc1bgaRGPP/rlwTZwMPims8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=p3JpvQq3; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=m3QbvnNT; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="p3JpvQq3"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="m3QbvnNT" Date: Wed, 19 Mar 2025 11:04:02 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1742382243; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pisNHpPgtLpXDkr778GBfvG3TrC4IUJDH7NxZiWuXy0=; b=p3JpvQq3O2U2Of0dbrD9K+J2P9cTydvi1l1SIQ+eVg9+5TRjYVg2YRcLDi5icFPjRCxOwu o+zl5LA98Q+Z8LQs8ynaeLxwBd/HYBMTVhX5A44lBfwcEZ6gal6BJZi/QfZ40smBhlHPy1 9MtxAgsL/2R2FWbTbazICxTCiIOKVaE6HOwtKTUO7HxFgWt5SOtyCE2zcuPn932XKnHgjb E39B0rqUgkJtBctJ6wktzeyU0nU6PE/1UGpUs72bzX1o32VG1seR3jTVym5PS7lbZCwXgs Ys008j4DrQkNaz7sHYUGR8Aave7U+gaXLyOGeM3Wl6r93aggf8M36wsTW8FyfQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1742382243; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pisNHpPgtLpXDkr778GBfvG3TrC4IUJDH7NxZiWuXy0=; b=m3QbvnNT5hVCGHA5rx7npOhn0v6HXFtl4YJn/ErKBSm30hfFqhE9v95+SyAaxjtxVZks7q vnZ2SEuHZlPQqZDw== From: "tip-bot2 for Rik van Riel" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/core] x86/mm: Enable AMD translation cache extensions Cc: Rik van Riel , "Borislav Petkov (AMD)" , Ingo Molnar , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250226030129.530345-13-riel@surriel.com> References: <20250226030129.530345-13-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174238224295.14745.16808184708471150955.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/core branch of tip: Commit-ID: 440a65b7d25fb06f85ee5d99c5ac492d49a15370 Gitweb: https://git.kernel.org/tip/440a65b7d25fb06f85ee5d99c5ac492d4= 9a15370 Author: Rik van Riel AuthorDate: Tue, 25 Feb 2025 22:00:47 -05:00 Committer: Ingo Molnar CommitterDate: Wed, 19 Mar 2025 11:12:29 +01:00 x86/mm: Enable AMD translation cache extensions With AMD TCE (translation cache extensions) only the intermediate mappings that cover the address range zapped by INVLPG / INVLPGB get invalidated, rather than all intermediate mappings getting zapped at every TLB invalidat= ion. This can help reduce the TLB miss rate, by keeping more intermediate mappin= gs in the cache. >From the AMD manual: Translation Cache Extension (TCE) Bit. Bit 15, read/write. Setting this bit= to 1 changes how the INVLPG, INVLPGB, and INVPCID instructions operate on TLB entries. When this bit is 0, these instructions remove the target PTE from = the TLB as well as all upper-level table entries that are cached in the TLB, whether or not they are associated with the target PTE. When this bit is s= et, these instructions will remove the target PTE and only those upper-level entries that lead to the target PTE in the page table hierarchy, leaving unrelated upper-level entries intact. [ bp: use cpu_has()... I know, it is a mess. ] Signed-off-by: Rik van Riel Signed-off-by: Borislav Petkov (AMD) Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20250226030129.530345-13-riel@surriel.com --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/amd.c | 4 ++++ tools/arch/x86/include/asm/msr-index.h | 2 ++ 3 files changed, 8 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 72765b2..1aacd6b 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -25,6 +25,7 @@ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ +#define _EFER_TCE 15 /* Enable Translation Cache Extensions */ #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ =20 #define EFER_SCE (1<<_EFER_SCE) @@ -34,6 +35,7 @@ #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) +#define EFER_TCE (1<<_EFER_TCE) #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) =20 /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 351c030..79569f7 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1075,6 +1075,10 @@ static void init_amd(struct cpuinfo_x86 *c) =20 /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); + + /* Enable Translation Cache Extension */ + if (cpu_has(c, X86_FEATURE_TCE)) + msr_set_bit(MSR_EFER, _EFER_TCE); } =20 #ifdef CONFIG_X86_32 diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/includ= e/asm/msr-index.h index 3ae84c3..dc1c105 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -25,6 +25,7 @@ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ +#define _EFER_TCE 15 /* Enable Translation Cache Extensions */ #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ =20 #define EFER_SCE (1<<_EFER_SCE) @@ -34,6 +35,7 @@ #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) +#define EFER_TCE (1<<_EFER_TCE) #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) =20 /*