From nobody Thu Dec 18 12:32:38 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0E90259CBF; Wed, 19 Mar 2025 11:03:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742382230; cv=none; b=B5EJMtk6D0jgG4fYZg+EEYLfRiDwW+ZgI5SZ0WfuondrSTndN2DOtD3Iqy9jJX5Zr73HI0awNZmRCak9YRtTSOIkQ4v9zbGmYBERuW3r5g7+/Ys8yBw+1HAE9nZR1WgIn6gflB7dLXjGUMgTs3jCpJHzJXwXHOlRpVL1SBEiUhI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742382230; c=relaxed/simple; bh=W5AxF6ogtm2tqkPxFiB4zFiM1jaQcD0LXgmETBReXX8=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=CtN54ne/lB0fwunZDhQFTtpTtAAoEKgsITTn+LEBZgjnLwWWwZx4IvHDbRPRTqLF/4PDcrXUP1wtH6snuH9fNsimyAtUGu+q49E73aCrRs6Q7MyV033aZJDSqgtt7crrVM2b1IMQ3K15gPp+cNAE/sY9nrdZBwtU/BeKNWuX5tU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=a0/QiTc1; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=yQ3BIIMg; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="a0/QiTc1"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="yQ3BIIMg" Date: Wed, 19 Mar 2025 11:03:45 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1742382226; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CiIigZ4KtN2ZDvJS9mwTAtyyFqgfSX0+n0o/eDbicN8=; b=a0/QiTc150+Ya3Jyd4TSe2XCMG+P0kdxgasgq0afqDB91ZsJL6UX3bLF2xbLk+QIxMiqPd oNEDp5063HAyISbfKlwz+Dj4qQVdY5rG4dCW7qKGdJeoz6sy7m+2BWNoyDpvRpMlXsNAZ8 rJsCAHfkkeL6KxoEHGm/UNz0HH3T9FmvWCyoZwVaaCtY88JNG/5KrE8Vo0SyfQ4rHN5jBX +p9tmXt3zDSUHt6jsbnj7UZoRUdjN30DYngK0cSEz7A7OO41P/NsfEGC5HP/K4t+psVRu3 if0Rm+42dqvGVqsdPtkarVkuOZf9UQM1V0HV7qX5NPOFcnUCMtdgolJb5pby1g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1742382226; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CiIigZ4KtN2ZDvJS9mwTAtyyFqgfSX0+n0o/eDbicN8=; b=yQ3BIIMgdpe6POMwYl7ddyVmnqYQD494MQV6A2AaMFHBkVF+KVbRjLmLZ1bvJUBeO2NAsm G7VA8rTlYnBQubCg== From: "tip-bot2 for Ingo Molnar" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/core] x86/cpuid: Standardize on u32 in Cc: Ingo Molnar , "Xin Li (Intel)" , Andrew Cooper , "H. Peter Anvin" , John Ogness , "Ahmed S. Darwish" , x86-cpuid@lists.linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250317221824.3738853-5-mingo@kernel.org> References: <20250317221824.3738853-5-mingo@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174238222532.14745.3385180566461540741.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/core branch of tip: Commit-ID: cfb4fc5f089a90b44832656ebe4504fcc41058ea Gitweb: https://git.kernel.org/tip/cfb4fc5f089a90b44832656ebe4504fcc= 41058ea Author: Ingo Molnar AuthorDate: Mon, 17 Mar 2025 23:18:23 +01:00 Committer: Ingo Molnar CommitterDate: Wed, 19 Mar 2025 11:19:26 +01:00 x86/cpuid: Standardize on u32 in Convert all uses of 'unsigned int' to 'u32' in . This is how a lot of the call sites are doing it, and the two types are equivalent in the C sense - but 'u32' better expresses that these are expressions of an immutable hardware ABI. Signed-off-by: Ingo Molnar Reviewed-by: Xin Li (Intel) Cc: Andrew Cooper Cc: "H. Peter Anvin" Cc: John Ogness Cc: "Ahmed S. Darwish" Cc: x86-cpuid@lists.linux.dev Link: https://lore.kernel.org/r/20250317221824.3738853-5-mingo@kernel.org --- arch/x86/include/asm/cpuid/api.h | 40 +++++++++++++++---------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index f26926b..356db18 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -22,8 +22,8 @@ static inline bool have_cpuid_p(void) } #endif =20 -static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, - unsigned int *ecx, unsigned int *edx) +static inline void native_cpuid(u32 *eax, u32 *ebx, + u32 *ecx, u32 *edx) { /* ecx is often an input as well as an output. */ asm volatile("cpuid" @@ -36,9 +36,9 @@ static inline void native_cpuid(unsigned int *eax, unsign= ed int *ebx, } =20 #define NATIVE_CPUID_REG(reg) \ -static inline unsigned int native_cpuid_##reg(unsigned int op) \ +static inline u32 native_cpuid_##reg(u32 op) \ { \ - unsigned int eax =3D op, ebx, ecx =3D 0, edx; \ + u32 eax =3D op, ebx, ecx =3D 0, edx; \ \ native_cpuid(&eax, &ebx, &ecx, &edx); \ \ @@ -65,9 +65,9 @@ NATIVE_CPUID_REG(edx) * Clear ECX since some CPUs (Cyrix MII) do not set or clear ECX * resulting in stale register contents being returned. */ -static inline void cpuid(unsigned int op, - unsigned int *eax, unsigned int *ebx, - unsigned int *ecx, unsigned int *edx) +static inline void cpuid(u32 op, + u32 *eax, u32 *ebx, + u32 *ecx, u32 *edx) { *eax =3D op; *ecx =3D 0; @@ -75,9 +75,9 @@ static inline void cpuid(unsigned int op, } =20 /* Some CPUID calls want 'count' to be placed in ECX */ -static inline void cpuid_count(unsigned int op, int count, - unsigned int *eax, unsigned int *ebx, - unsigned int *ecx, unsigned int *edx) +static inline void cpuid_count(u32 op, int count, + u32 *eax, u32 *ebx, + u32 *ecx, u32 *edx) { *eax =3D op; *ecx =3D count; @@ -88,43 +88,43 @@ static inline void cpuid_count(unsigned int op, int cou= nt, * CPUID functions returning a single datum: */ =20 -static inline unsigned int cpuid_eax(unsigned int op) +static inline u32 cpuid_eax(u32 op) { - unsigned int eax, ebx, ecx, edx; + u32 eax, ebx, ecx, edx; =20 cpuid(op, &eax, &ebx, &ecx, &edx); =20 return eax; } =20 -static inline unsigned int cpuid_ebx(unsigned int op) +static inline u32 cpuid_ebx(u32 op) { - unsigned int eax, ebx, ecx, edx; + u32 eax, ebx, ecx, edx; =20 cpuid(op, &eax, &ebx, &ecx, &edx); =20 return ebx; } =20 -static inline unsigned int cpuid_ecx(unsigned int op) +static inline u32 cpuid_ecx(u32 op) { - unsigned int eax, ebx, ecx, edx; + u32 eax, ebx, ecx, edx; =20 cpuid(op, &eax, &ebx, &ecx, &edx); =20 return ecx; } =20 -static inline unsigned int cpuid_edx(unsigned int op) +static inline u32 cpuid_edx(u32 op) { - unsigned int eax, ebx, ecx, edx; + u32 eax, ebx, ecx, edx; =20 cpuid(op, &eax, &ebx, &ecx, &edx); =20 return edx; } =20 -static inline void __cpuid_read(unsigned int leaf, unsigned int subleaf, u= 32 *regs) +static inline void __cpuid_read(u32 leaf, u32 subleaf, u32 *regs) { regs[CPUID_EAX] =3D leaf; regs[CPUID_ECX] =3D subleaf; @@ -141,7 +141,7 @@ static inline void __cpuid_read(unsigned int leaf, unsi= gned int subleaf, u32 *re __cpuid_read(leaf, 0, (u32 *)(regs)); \ } =20 -static inline void __cpuid_read_reg(unsigned int leaf, unsigned int sublea= f, +static inline void __cpuid_read_reg(u32 leaf, u32 subleaf, enum cpuid_regs_idx regidx, u32 *reg) { u32 regs[4];